IEEE Symposium on VLSI Technology

IEEE Symposium on VLSI Technology
Name	IEEE Symposium on VLSI Technology
Discipline	Microelectronics; VLSI
Abbreviation	VLSI Symposium
Publisher	Institute of Electrical and Electronics Engineers
Frequency	Annual
First	1981
Country	International

IEEE Symposium on VLSI Technology The IEEE Symposium on VLSI Technology is an annual peer-reviewed forum for advances in VLSI and microelectronics research, bringing together authors, engineers, and academics from institutions such as Stanford University, Massachusetts Institute of Technology, University of California, Berkeley, Tsinghua University, and National University of Singapore. The symposium complements related meetings like the International Solid-State Circuits Conference, Design Automation Conference, Symposium on VLSI Circuits, and International Conference on Computer-Aided Design. Corporate participants often include Intel, TSMC, Samsung Electronics, GlobalFoundries, and IBM Research.

History

Established in the early 1980s amid rapid scaling following Moore's law trends and milestones at Bell Labs and Fairchild Semiconductor, the symposium emerged to highlight process technology, device physics, and integration advances developed at laboratories such as HP Labs and Bellcore. Early organizers included researchers affiliated with Caltech, University of Illinois Urbana-Champaign, and Carnegie Mellon University, and the meeting paralleled developments at the IEEE Electron Devices Society and conferences like IEDM. Over decades the symposium documented transitions from CMOS scaling through FinFET adoption, the rise of 3D ICs, and exploratory work in carbon nanotube devices and spintronics. Venues have rotated among locations including Honolulu, Kyoto, San Francisco, Hawaii, Kyoto Protocol-adjacent meeting sites, and major academic hubs in Tokyo and Seoul.

Scope and Topics

The symposium covers fabrication and process integration topics spanning CMOS technology nodes, lithography advances related to extreme ultraviolet lithography, device architectures such as FinFET, Gate-All-Around FET, and materials research into high-k dielectrics, hafnium dioxide, graphene, and transition metal dichalcogenides. Papers often address interconnect challenges tied to copper interconnects, low-k dielectrics, and electromigration, as well as reliability studies referencing phenomena documented by JEDEC and International Technology Roadmap for Semiconductors reports. Cross-disciplinary submissions connect to thermal management work from MIT groups, packaging advances like through-silicon vias, heterogeneous integration exemplified by chiplet ecosystems, and measurements related to scanning electron microscope and transmission electron microscope analysis performed in facilities such as Lawrence Berkeley National Laboratory and Argonne National Laboratory.

Conference Format and Organization

Organized under the aegis of the IEEE, program committees composed of members from University of Texas at Austin, Cornell University, Peking University, ETH Zurich, and Imperial College London manage peer review, tutorials, and poster sessions. The symposium features invited keynotes from leaders at Intel Corporation, Samsung Electronics, TSMC, Sony, NVIDIA, and research institute directors from IMEC and CSEM. Review processes follow single-blind or double-blind traditions similar to those used by SIGGRAPH and NeurIPS, while tutorial tracks echo formats seen at ACM workshops. Tutorial organizers coordinate with industrial exhibitors from Applied Materials, ASML, Lam Research, and foundry partners for demonstrations and short courses.

Notable Papers and Contributions

The symposium has hosted seminal reports on device scaling limits, including early FinFET characterizations that influenced Intel and TSMC roadmaps, innovations in strain engineering adopted by GlobalFoundries, and demonstrations of novel channel materials that informed follow-on work at IBM Research and Samsung Advanced Institute of Technology. Landmark contributions include studies on gate dielectric reliability cited alongside work from SEMATECH and IMEC, interconnect scaling analyses aligned with observations from Kalpana L. Srivastava-affiliated groups, and 3D integration demonstrations that paralleled efforts at Xilinx and AMD. Results presented at the symposium frequently appear in extended form in journals such as IEEE Transactions on Electron Devices, Applied Physics Letters, and Nature Electronics, and are referenced by standards bodies like IEC and JEDEC.

Awards and Recognitions

The symposium confers best paper awards and recognitions honoring impactful contributions, with recipients often later receiving distinctions such as the IEEE Medal of Honor, Semiconductor Research Corporation awards, and fellowships in IEEE and ACM. Notable awardees have included researchers associated with Stanford University, UC Berkeley, Seoul National University, Delft University of Technology, and contributors from industrial labs including Intel Labs and IBM Research. Honorary lectures and industry recognition sessions feature award presentations tied to achievement lists similar to the IEEE Fellow nominations and national honors in countries such as Japan, Germany, and the United States.

Sponsorship and Affiliated Events

Primary sponsorship is provided by the IEEE and the IEEE Electron Devices Society, with institutional support from universities like Stanford University, University of California, and University of Tokyo, and corporate support from Intel, TSMC, Samsung Electronics, ASML, and Applied Materials. Affiliated events include workshops co-located with IEDM, short courses resonant with VLSI Symposia programs, and panels coordinated with bodies such as SEMICON and Semiconductor Research Corporation. Regional satellite events and summer schools leverage partnerships with NSF, EU Horizon 2020 projects, and national agencies including DARPA and MEXT.

Category:IEEE conferences