Symposium on VLSI Technology

Symposium on VLSI Technology
Institute of Electrical and Electronics Engineers · Public domain · source
Name	Symposium on VLSI Technology
Abbreviation	VLSI Symp.
Discipline	Very-large-scale integration
Frequency	Annual
First	1980s
Venue	Various
Country	International
Organized by	IEEE Computer Society / IEEE Electron Devices Society / Japan Society of Applied Physics

Symposium on VLSI Technology The Symposium on VLSI Technology is an annual technical conference dedicated to Very-large-scale integration research, fabrication, and devices. The symposium convenes researchers from Intel Corporation, TSMC, Samsung Electronics, Tokyo Institute of Technology, Stanford University, and University of California, Berkeley to present peer-reviewed advances in semiconductor process technologies, device architectures, and characterization. Proceedings often influence roadmap discussions at International Technology Roadmap for Semiconductors-related forums and inform design strategies used by NVIDIA, AMD, Apple Inc., and Qualcomm.

Overview

The symposium focuses on scaling and integration challenges for CMOS and emerging device technologies such as FinFET, Gate-all-around transistor, 2D materials, graphene, and carbon nanotube devices. Sessions attract engineers from foundries like GlobalFoundries and UMC and academic groups from Massachusetts Institute of Technology, University of Cambridge, Swiss Federal Institute of Technology in Zurich, and Peking University. Key topics span lithography techniques including extreme ultraviolet lithography, interconnects studied by IBM Research, and memory technologies researched at Micron Technology. The event is frequently co-located with workshops on reliability and testing attended by members of JEDEC and SEMATECH.

History and Development

The symposium emerged amid rapid miniaturization driven by companies such as Intel Corporation and research labs at Bell Labs during the microelectronics expansion of the late 20th century. Early conferences documented transitions from NMOS and CMOS scaling to metal-oxide-semiconductor innovations and chronicled contributions from researchers at Bell Labs, Hewlett-Packard, and Fairchild Semiconductor. Throughout the 1990s and 2000s the symposium mirrored industry shifts led by Moses Tai, Gordon Moore, and development programs at Texas Instruments and Advanced Micro Devices. In the 2010s the meeting adapted to new paradigms introduced by DARPA programs, collaborations with Japan Society for the Promotion of Science, and alliances among European Commission research projects. Recent years have emphasized heterogenous integration investigated by ASE Group and three-dimensional stacking advanced by TSMC and Intel Foundry Services.

Conference Topics and Technical Scope

The technical scope covers device physics, process technology, characterization methods, and circuit implications of scaled technologies. Typical categories include transistor architecture studies referencing Robert Noyce-era device scaling, dielectric materials explored at Corning Incorporated, interconnect metallization discussed by Lam Research-affiliated teams, and yield enhancement methods pursued by KLA Corporation. Sessions feature experimental reports on mobility in MoS2 and WSe2 from groups at University of California, Los Angeles and National Tsing Hua University, alongside modeling efforts from Sandia National Laboratories and Lawrence Berkeley National Laboratory. Lithography and patterning coverage involves contributions related to ASML tools, resist chemistry, and metrology developed at National Institute of Standards and Technology.

Notable Papers and Contributions

Historically influential papers presented at the symposium have included early demonstrations of FinFET performance improvements, gate dielectric scaling approaches paralleling IBM Research milestones, and reports on novel channel materials such as III-V semiconductors and transition metal dichalcogenides. Landmark presentations by researchers affiliated with Stanford University, Tsinghua University, Seoul National University, and University of Tokyo have shaped transistor roadmaps and spurred collaborations with industry partners like Samsung Advanced Institute of Technology and Intel Labs. Contributions on low-power design and leakage control informed standards used by ARM Holdings licensees, while works on nonvolatile memory impacted SK Hynix and Toshiba product directions.

Organization and Sponsorship

Organized by committees composed of representatives from IEEE chapters, major foundries, and academic institutions, the symposium receives sponsorship from corporations including Intel Corporation, Samsung Electronics, TSMC, Micron Technology, and equipment vendors such as ASML and Applied Materials. Program committees often include members from IEEE Electron Devices Society and editorial contributors to journals like IEEE Transactions on Electron Devices. Collaboration with regional societies such as Japan Society of Applied Physics and funding or endorsement from agencies including National Science Foundation or Ministry of Economy, Trade and Industry (Japan) is common for workshop co-sponsorship.

Awards and Recognition

The symposium bestows awards for Best Paper, Best Student Paper, and recognition for lifetime technical contributions similar in prestige to honors from IEEE societies and awards like the Ebers Award and IEEE Daniel E. Noble Award in relevance. Recipients frequently include researchers from Cornell University, Imperial College London, Nanyang Technological University, and industrial labs at IBM and Intel, whose recognized work often appears later in journals such as Nature Electronics and IEEE Journal of Solid-State Circuits.

Attendance and Impact on Industry and Academia

Attendance comprises senior technologists from GlobalFoundries, graduate students from Carnegie Mellon University, and policy-influencing attendees from agencies such as DARPA and European Research Council. Proceedings and presentations inform product roadmaps at Apple Inc., NVIDIA, and Broadcom Inc. and curricula at universities including University of Illinois Urbana–Champaign and Delft University of Technology. The symposium fosters collaborations resulting in cross-institutional projects with funding from European Union Horizon 2020, technology transfer involving Tsinghua University spin-offs, and standards contributions incorporated by JEDEC and other consortia.

Category:Semiconductor conferences