gate-all-around transistor

gate-all-around transistor
Name	Gate-all-around transistor
Caption	Cross-section schematic of a multibridge nanowire gate-all-around device
Type	Field-effect transistor
Introduced	2010s
Developer	Intel, TSMC, Samsung Electronics
Gate	Surrounding gate
Channel	Nanowire, nanosheet
Application	Semiconductor device fabrication, Integrated circuits

gate-all-around transistor The gate-all-around transistor is a class of field-effect transistor architecture in which the gate electrode encloses the channel on all sides to improve electrostatic control, reduce leakage, and enable further miniaturization. Developed as an evolution of the Metal–oxide–semiconductor field-effect transistor and FinFET architectures, it has been pursued by major foundries such as Intel, TSMC, and Samsung Electronics for sub-10 nm process nodes. Research milestones and commercialization efforts have involved collaborations among institutions like IMEC, Applied Materials, and university groups at Stanford University, Massachusetts Institute of Technology, and Tsinghua University.

Introduction

Gate-all-around transistors extend concepts from the planar transistor era and the three-dimensional FinFET to a fully surrounding gate topology, realized as stacked nanowires or nanosheets that allow the gate to modulate the channel from every lateral and vertical direction. Early academic demonstrations and process-roadmap evaluations appeared in publications from Intel Corporation Research, University of California, Berkeley, and IMEC, with design studies presented at International Electron Devices Meeting and Symposium on VLSI Technology. Industry roadmaps such as the International Technology Roadmap for Semiconductors and its successor organizations guided the shift toward gate-all-around as node scaling pushed beyond the limits of conventional complementary metal–oxide–semiconductor scaling trajectories.

Design and Operation

The gate-all-around device encloses a cylindrical or rectangular channel—often realized as a vertical nanowire, horizontal nanosheet, or multibridge string—allowing the gate stack to surround the channel fully and create superior electrostatic control compared with planar MOSFETs and FinFETs. Operating principles rely on modulation of carrier density in the channel by the gate workfunction and dielectric engineering, integrating materials studied at Bell Labs and modeled in simulations from Sandia National Laboratories and Lawrence Berkeley National Laboratory. Device variants explore channel materials such as silicon, germanium, and III-V compounds like gallium arsenide and indium gallium arsenide to optimize mobility and drive current, with gate stacks employing high-κ dielectrics pioneered by Intel and Samsung Electronics.

Fabrication and Materials

Fabrication flows derive from process innovations in lithography, etch, deposition, and planarization techniques developed at ASML Holding, Applied Materials, and Lam Research. Typical sequences include definition of sacrificial layers, selective etch of channel-release materials, replacement-metal-gate processes, and atomic-layer deposition of high-κ films—methods refined at facilities including Taiwan Semiconductor Manufacturing Company fabs and the GlobalFoundries ecosystem. Materials research draws on heterostructure and epitaxy expertise from Nikon Corporation collaborations and university groups at Purdue University and University of Illinois Urbana–Champaign, while packaging and thermal-management solutions intersect with work at Intel Foundry Services and TSMC testing sites.

Performance and Scaling Advantages

Gate-all-around designs reduce short-channel effects, subthreshold slope degradation, and off-state leakage compared with FinFET counterparts, supporting continued transistor-density scaling targeted by the International Roadmap for Devices and Systems. The surrounding gate enables steeper subthreshold slopes and improved threshold-voltage control, demonstrated in benchmarking studies at IBM Research, Samsung Research, and KAIST. These devices facilitate multiple-channel stacks to increase effective width-per-footprint, aligning with efforts by Apple Inc. for mobile SoC performance and NVIDIA in high-performance computing accelerators. Simulations and measured data from TSMC and Intel show benefits for static power and switching energy relevant to datacenter operators such as Google and Amazon Web Services.

Challenges and Limitations

Adoption faces challenges including complex process integration, yield sensitivity, and variability tied to nanoscale line-edge roughness and etch selectivity issues documented in studies from IMEC and Fraunhofer Society. Fabrication of uniform nanowires or nanosheets across large wafers stresses lithography capabilities from ASML and precursor control in chemical vapor deposition programs at Applied Materials. Material and reliability concerns—gate dielectric integrity, hot-carrier degradation, and thermal dissipation in densely stacked channels—have been subjects of reliability testing by JEDEC committees and failure-analysis teams at Intel and Samsung Electronics. Supply-chain and capital-cost implications influence foundry roadmaps managed by TSMC and GlobalFoundries.

Applications and Commercial Adoption

Gate-all-around transistors are being deployed for advanced logic in leading-edge process nodes by Samsung Electronics and TSMC, with announcements by Intel describing imminent transitions in their process roadmap. Target markets include high-performance microprocessors for companies like AMD and Intel; mobile application processors for Qualcomm and Apple Inc.; and accelerators for NVIDIA and hyperscale datacenter operators such as Microsoft and Google. Beyond logic, research explores integration into mixed-signal and RF front-end modules developed by vendors including Broadcom and Skyworks Solutions, and potential synergies with emerging packaging standards promoted by JEDEC and the Open Compute Project. Continued collaboration among academic institutions, national labs, and industry consortia sustains roadmap progress toward future nodes.

Category:Transistors