magnetoresistive random-access memory

magnetoresistive random-access memory
Name	Magnetoresistive random-access memory
Type	Non-volatile memory
Invented	1980s
Inventor	Albert Fert, Peter Grünberg
Developers	IBM, Samsung Electronics, Intel Corporation, Toshiba
Interface	Electrical
Use	Embedded systems, storage-class memory

magnetoresistive random-access memory is a non-volatile memory technology that stores information using magnetic states rather than charge, combining features of Dynamic random-access memory, Flash memory, and Static random-access memory. It emerged from discoveries in spintronics and magnetoresistance during the late 20th century and has been pursued by companies and institutions such as IBM Research, Samsung Electronics, Intel Corporation, and Toshiba for applications ranging from embedded systems to potential storage-class memory. Research programs at universities and national labs including Massachusetts Institute of Technology, Stanford University, University of California, Berkeley, Hitachi, and Seagate Technology have driven materials, device, and circuit-level advances.

Introduction

MRAM traces roots to fundamental work on the Giant magnetoresistance effect by Albert Fert and Peter Grünberg, which led to applications in hard disk drive read heads and later to spintronic memory concepts. Early MRAM prototypes were demonstrated by industrial groups such as IBM, Toshiba, and Grand Hall research partnerships, while standards and commercialization efforts involved JEDEC, ARM Holdings, and major foundries like TSMC. The technology competes with incumbent memories produced by Samsung Electronics, Micron Technology, and SK Hynix and has been integrated into products from vendors including Infineon Technologies and Everspin Technologies.

Principles and Device Physics

At its core MRAM exploits phenomena from spintronics including Tunneling magnetoresistance and spin-transfer torque, built on multilayer stacks such as magnetic tunnel junctions (MTJs) comprised of ferromagnetic layers (e.g., Cobalt, Iron, Nickel) separated by thin oxides like Magnesium oxide. Writing schemes use mechanisms derived from Spin-transfer torque and Spin–orbit torque concepts, related to discoveries from groups at University of Groningen and Université Paris-Saclay; readout relies on tunnel magnetoresistance ratios characterized in studies at National Institute of Standards and Technology and European Research Council-funded consortia. Device models borrow from transport theory developed by researchers associated with Bell Labs, Los Alamos National Laboratory, and Argonne National Laboratory to account for phenomena such as magnetic anisotropy, thermal stability (linked to Néel relaxation and Brown's theory), and Gilbert damping characterized by parameters reported in papers from Cornell University and University of Cambridge.

Architecture and Fabrication

Commercial MRAM arrays employ CMOS back-end-of-line integration with MTJ stacks fabricated using processes developed at fabs like TSMC and GlobalFoundries and design rules influenced by International Technology Roadmap for Semiconductors initiatives. Architectures include toggle-MRAM designs pioneered by Fujitsu and spin-transfer-torque MRAM (STT-MRAM) promoted by Samsung Electronics and Intel Corporation, with variations such as perpendicular magnetic anisotropy configurations studied at University of Tokyo and Seoul National University. Fabrication challenges involve patterning at nodes used by Intel Corporation and AMD for embedded memory, deposition techniques advanced by equipment suppliers like Applied Materials and ASML Holding, and encapsulation tested in cleanrooms operated by institutions such as IMEC and CEA-Leti. Peripheral circuitry borrows IP from companies including Synopsys and Cadence Design Systems for sense amplifiers, write drivers, and error-correction schemes used by suppliers like Microchip Technology.

Performance Characteristics and Comparisons

MRAM delivers non-volatility with endurance and speed characteristics that position it between SRAM and Flash memory; STT-MRAM variants achieve read/write latencies comparable to SRAM in some embedded use cases and endurance superior to NAND flash as demonstrated in benchmarking by JEDEC-aligned labs and corporations including Everspin Technologies. Metrics such as switching current density, retention time, and tunnel magnetoresistance ratio are routinely compared in reviews from IEEE, Nature Electronics, and conferences like International Electron Devices Meeting and IEEE Symposium on VLSI Technology. Power consumption profiles have been evaluated against low-power solutions from ARM Holdings and energy-efficiency studies at Lawrence Berkeley National Laboratory show trade-offs involving write energy and device scaling. System-level comparisons to emerging memories like Resistive RAM, Phase-change memory, and Ferroelectric RAM have been part of roadmaps published by European Semiconductor Industry Association and U.S. Department of Defense research programs.

Applications and Industry Adoption

Adoption of MRAM has been strongest in embedded applications where companies such as Infineon Technologies, Renesas Electronics, and STMicroelectronics have shipped parts for microcontrollers, power management, and networking equipment. Standalone devices from Everspin Technologies target industrial, aerospace, and automotive markets with parts qualified to standards maintained by Automotive Electronics Council and tested under regimes used by NASA and European Space Agency. MRAM has been proposed for cache hierarchies in servers by firms like Intel Corporation and for storage-class memory in hybrid systems designed by Hewlett Packard Enterprise and Dell Technologies, with pilots conducted at research centers including Sandia National Laboratories and Riken.

Challenges and Future Developments

Key challenges include scaling write current and variability issues faced at process nodes used by TSMC and Samsung Electronics, integration of novel materials researched at Max Planck Institute for Microstructure Physics and Paul Scherrer Institute, and manufacturing yield considerations addressed by Apple Inc. supply-chain partners. Advances in voltage-controlled magnetic anisotropy, multi-level cell concepts studied at University of Illinois Urbana-Champaign, and hybrid architectures combining MRAM with Compute Express Link-enabled fabrics indicate pathways pursued by consortiums involving Google, Microsoft, and Amazon Web Services. Future developments are likely to be shaped by collaborations among foundries like GlobalFoundries, consortia such as SEMATECH, and funding from agencies including European Commission and National Science Foundation to push MRAM toward wider adoption in consumer and data-center markets.

Category:Non-volatile memory