Static random-access memory

Static random-access memory
Satyamfifa · Public domain · source
Name	Static random-access memory
Type	Semiconductor memory
Invented	1960s
Inventor	Robert H. Dennard, John Bardeen, Walter Brattain
Density	Low compared with Dynamic random-access memory
Access time	Typically 1–10 ns
Voltage	Technology dependent

Static random-access memory is a semiconductor memory technology used for high-speed data storage in electronic systems. It stores data using bistable latching circuitry and provides faster access than Dynamic random-access memory while trading off density and cost. SRAM is widely used in cache hierarchies, embedded systems, and networking equipment designed by organizations such as Intel Corporation, ARM Holdings, and NVIDIA Corporation.

Definition and basic operation

SRAM is a form of volatile semiconductor memory where each bit is held in a bistable circuit, typically a cross-coupled pair of transistor switches. Inventive work by researchers at institutions like IBM and Texas Instruments contributed alongside pioneers such as Robert H. Dennard, with foundational transistor research by John Bardeen and Walter Brattain laying groundwork for solid-state memory. A cell maintains its state as long as power is applied, and read/write operations occur via bit line and word line interactions coordinated by peripheral circuits implemented in technologies used by companies like TSMC and GlobalFoundries.

Circuit design and cell topology

Common topologies include six-transistor (6T), four-transistor (4T), and one-transistor one-capacitor variants developed through collaboration among researchers at Bell Labs, Stanford University, and MIT. The ubiquitous 6T cell uses complementary pairs of MOSFET devices in cross-coupled inverters with access transistors controlled by the word line; peripheral sense amplifiers from firms such as Analog Devices and Maxim Integrated detect small voltage differentials on bit lines. Alternative designs—such as embedded SRAM cells in microcontrollers by Microchip Technology—exploit custom transistor sizing strategies pioneered at UC Berkeley and Carnegie Mellon University.

Performance characteristics and comparisons

SRAM offers low access latency and high bandwidth compared with Dynamic random-access memory and Flash memory technologies used by vendors like Samsung Electronics and Micron Technology. Cache hierarchies in processors from Intel Corporation and AMD rely on multi-level SRAM arrays to achieve performance targets set by architectures influenced by work at ARM Holdings and projects like RISC-V. Compared to non-volatile memories such as EEPROM and NAND flash, SRAM trades persistence for speed and endurance, positioning it alongside specialized memories like Content-addressable memory in high-performance networking platforms produced by companies like Cisco Systems.

Fabrication and technology scaling

SRAM scaling has followed CMOS process node advancements at foundries including TSMC, Intel Corporation, and Samsung Electronics, with cell size reductions driven by innovations from institutions like IMEC and CEA-Leti. Design-for-manufacturability techniques developed in collaboration with Synopsys and Cadence Design Systems address variability introduced at advanced nodes such as 14 nm, 7 nm, and 5 nm. Process innovations—finFET structures championed by Intel Corporation and TSMC—affect threshold voltages and leakage currents, leading to novel cell variants and support IP from suppliers like Arm Me P}}.

Applications and use cases

SRAM is central to CPU cache implementations in processors from Intel Corporation, AMD, and ARM Holdings, and to on-chip buffers in networking gear by Cisco Systems and Juniper Networks. Graphics processors by NVIDIA Corporation and AMD use SRAM for register files and cache tiles, while embedded microcontrollers from Microchip Technology and STMicroelectronics integrate SRAM for real-time control. Other applications include telecommunications equipment by Ericsson and Nokia, automotive controllers by Bosch and Continental AG, and aerospace avionics designed by Honeywell International.

Power consumption and retention

SRAM consumes static power due to leakage in idle states and dynamic power during read/write cycles; power characteristics are influenced by transistor models evolved from work at Bell Labs and Fairchild Semiconductor. Low-power SRAM variants targeted at mobile platforms by Qualcomm and Apple Inc. use voltage scaling and power gating strategies informed by research at University of Illinois Urbana-Champaign and UC Berkeley. Retention time is effectively infinite while powered, but power-optimized cells such as 8T or 10T retention cells implement isolation schemes used in system-on-chip designs from NXP Semiconductors and Texas Instruments.

Reliability, testing, and error mitigation

Reliability concerns—soft errors from ionizing radiation studied at CERN and NASA, and aging effects characterized by groups at SETA, Bell Labs and IMEC—lead to mitigation techniques like error-correcting codes used by IBM and HPE. Testing methodologies, boundary-scan and built-in self-test (BIST) tools from Teradyne and Advantest validate SRAM arrays post-fabrication, while redundancy, scrubbing, and fault-tolerant design practices influenced by standards bodies like IEEE and JEDEC are employed in mission-critical systems developed by Lockheed Martin and Raytheon Technologies.

Category:Computer memory