Dynamic random-access memory

Dynamic random-access memory
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Name	Dynamic random-access memory
Type	Semiconductor memory
Invented	1966
Inventor	Robert H. Dennard
First produced	1970s
Applications	Personal computers, servers, smartphones, embedded systems
Successors	Magnetoresistive RAM, Phase-change memory

Contents

Dynamic random-access memory Dynamic random-access memory (DRAM) is a type of semiconductor memory used as main system memory in Intel, AMD, Apple Inc., NVIDIA systems and in embedded designs by Qualcomm, Samsung Electronics, Micron Technology, SK Hynix. It stores each bit in a capacitor and requires periodic refresh, a design originating from work by Robert H. Dennard and commercialized during the era of IBM, Texas Instruments, Intel Corporation expansion and the rise of Personal Computer manufacturers like Compaq, Dell Technologies, Hewlett-Packard. DRAM underpins performance in platforms built by Microsoft, Google, Amazon (company), and supports workloads in data centers run by Facebook, Oracle Corporation, Alibaba Group.

Overview

DRAM is organized into arrays and accessed via controllers designed by companies such as ARM Holdings, Broadcom Inc., Marvell Technology Group, ASMedia Technology and used in systems from Lenovo, Acer Inc., Sony, LG Electronics. Early DRAM histories involve Fairchild Semiconductor, Intel Corporation and market shifts influenced by legal actions like those involving Federal Trade Commission and standards shaped alongside organizations such as JEDEC, International Electrotechnical Commission, IEEE. The product ecosystem includes modules built by Corsair, Kingston Technology, G.SKILL and factory fabs like TSMC, GlobalFoundries, UMC, Samsung Electronics.

DRAM cell arrays are arranged into rows and columns accessed by address decoders used in architectures from ARM, x86, RISC-V CPU platforms and memory controllers in chipsets by Intel Corporation, AMD, NVIDIA. The principal DRAM cell was proposed by Robert H. Dennard and relies on a transistor and capacitor pair similar to charge-storage concepts pursued at Bell Labs and RCA. Access timing involves signals specified in standards maintained by JEDEC and synchronized by system buses like PCI Express, DDR4, DDR5, and controlled in system firmware by teams at Microsoft, Apple Inc., Linux Foundation. Memory controllers interact with I/O subsystems designed by Cadence Design Systems, Synopsys, Altera (Intel) to manage refresh, activation, precharge, and rowhammer mitigation features developed by research groups at University of California, Berkeley, Massachusetts Institute of Technology, Stanford University.

DRAM families include SDRAM variants standardized through efforts by JEDEC and adopted by companies such as Samsung Electronics, Micron Technology, SK Hynix with types like DDR, DDR2, DDR3, DDR4, DDR5 used in systems from Dell Technologies, Apple Inc., Lenovo. Specialized forms such as LPDDR are used in mobile products from Qualcomm, Apple Inc., Samsung Electronics and high-bandwidth designs like HBM are integrated by AMD, NVIDIA, Intel Corporation for accelerators in systems deployed by Google, Microsoft Azure, Amazon Web Services. Emerging alternatives include non-volatile memories promoted by IBM, Intel Corporation, Micron Technology such as MRAM, ReRAM, Phase-change memory though mainstream replacement remains constrained by industry transitions led by fabs like TSMC and Samsung Foundry.

DRAM performance is characterized by latency and bandwidth parameters specified by standards bodies including JEDEC and implemented by module makers such as Kingston Technology, Crucial (Micron), Corsair. Timing constraints like CAS latency, RAS-to-CAS, and tREFI are managed by controllers from Intel Corporation, AMD, Arm Holdings and profiled by benchmarking tools from PCMark, PassMark Software, SiSoftware. System integrators such as HP Enterprises, Cisco Systems, Dell EMC tune memory parameters for workloads from Oracle Corporation databases, SAP SE applications, Apache Hadoop clusters and accelerators used in NVIDIA AI stacks, where throughput demands are driven by services from Google Cloud Platform, Microsoft Azure, Amazon Web Services.

Scaling DRAM density and voltage reductions are central to roadmaps from fabs like Samsung Electronics, SK Hynix, Micron Technology, and face lithography and process limits addressed by ASML extreme ultraviolet tools and collaborations involving Applied Materials, Lam Research. Market dynamics are affected by mergers and competition among firms such as Intel Corporation, AMD, Broadcom Inc. and geopolitical factors involving governments like United States Department of Commerce, European Commission, Ministry of Commerce (China). Yield, defect control, and cost-per-bit are managed in factories influenced by supply chains of companies like Foxconn, TSMC, GlobalFoundries with packaging advances including 2.5D and 3D stacking explored by Intel Foundry Services, TSMC.

DRAM is integral to systems produced by Apple Inc., Dell Technologies, Lenovo, HP Inc. and cloud infrastructure from Amazon.com, Google LLC, Microsoft Corporation enabling operating systems like Windows NT, macOS, Linux kernel, and virtualization platforms from VMware, KVM, Hyper-V. In consumer products, DRAM supports gaming consoles made by Sony Interactive Entertainment, Microsoft Xbox, and embedded systems by Texas Instruments, NXP Semiconductors. High-performance computing clusters at institutions such as Los Alamos National Laboratory, Lawrence Berkeley National Laboratory, CERN rely on DRAM capacity and bandwidth alongside interconnects from InfiniBand Trade Association, Mellanox Technologies.

DRAM reliability techniques such as ECC memory are provided by vendors like Micron Technology, Samsung Electronics, HPE and standardized in enterprise systems from IBM, Dell EMC, Oracle Corporation to protect workloads from errors analyzed by research teams at MIT, ETH Zurich, University of Cambridge. Error modes like rowhammer were investigated by groups at Carnegie Mellon University, Google Project Zero, University of California, Berkeley leading to mitigations implemented by Intel Corporation, AMD, ARM Holdings firmware updates and OS patches from Microsoft, Apple Inc., Canonical (company). Testing and qualification are performed using equipment from Teradyne, Advantest and facility certifications tied to standards from ISO and JEDEC.