RISC-V

RISC-V
Name	RISC-V
Introduced	2010
Type	Instruction set architecture
Status	Active

RISC-V is an open standard instruction set architecture developed to provide a free, extensible foundation for processor design. It emerged from academic research into reduced instruction set computing and has influenced semiconductor projects, startup ventures, university programs, and national initiatives. The specification has been used in a range of microcontroller, embedded, server, and research platforms and has attracted attention from corporations, consortia, and governments.

History

RISC-V traces origins to academic work at University of California, Berkeley, drawing on legacies from projects associated with Berkeley RISC, MIPS Technologies, ARM Holdings, DEC and the broader reduced instruction set computing movement exemplified by figures linked to John Cocke and David Patterson. Early formalization and releases involved contributors connected to SRI International, IBM, Intel, Google (company), NVIDIA and SiFive, and were contemporaneous with initiatives at DARPA and discussions in standards contexts alongside organizations such as IEEE and ISO. The project’s early dissemination coincided with academic dissemination at conferences like ISCA, ASPLOS, Micro (conference), and Hot Chips, and with textbooks and work by authors associated with ACM and IEEE Computer Society.

Architecture

The instruction set architecture defines a base integer ISA and optional extensions, with design principles informed by research from RISC I, RISC II, SPARC, Alpha (microprocessor), PowerPC, x86-64 discussions, and microarchitectural concepts that appear in literature tied to Amdahl's law and Dennard scaling. The modular ISA approach supports variants for 32-bit, 64-bit, and 128-bit address spaces and optional floating-point and vector extensions paralleling work by groups associated with IEEE 754 and vector proposals seen in projects involving Cray Research, NEC, and Fujitsu. Privilege levels, exception handling, memory model choices, and atomic operations reflect influences from standards and research produced by POSIX, Linux kernel, FreeBSD, Microsoft research, and academic groups at MIT and Stanford University. The architecture’s encoding and extension model have been discussed in venues including USENIX, SIGARCH, and by implementers such as ARM licensees, MIPS Technologies alumni, and engineers seconded from Qualcomm and Texas Instruments.

Implementations and Products

Commercial and academic implementations span companies and institutions such as SiFive, Western Digital, Alibaba Group, Baidu, Samsung Electronics, Qualcomm, NVIDIA, Intel, Xilinx, Microchip Technology, Analog Devices, Broadcom, LowRISC, Espressif Systems, GreenWaves Technologies, Gowin Semiconductor, Codasip, Syntacore, Andes Technology, STMicroelectronics, Renesas Electronics, Zhejiang University and university labs at ETH Zurich, Tsinghua University, Peking University, University of Cambridge and Cornell University. Products include microcontrollers, multicore SoCs, accelerators, FPGA soft cores, and research chips deployed at events like Hot Chips and Design Automation Conference. Implementations have been fabricated using processes associated with foundries like TSMC, GlobalFoundries, SMIC, Samsung Foundry and integrated into platforms shipping from vendors involved with Arduino, Raspberry Pi, BeagleBoard, Xilinx Zynq, and cloud initiatives by Amazon Web Services and Alibaba Cloud.

Software Ecosystem

Toolchain and software support includes contributions from projects and organizations such as GNU Project, LLVM Project, GCC, Binutils, GDB (software), QEMU, OpenOCD, Yocto Project, Buildroot, Debian, Fedora (operating system), Ubuntu, Red Hat, SUSE, Microsoft Azure, Google Cloud Platform and Amazon Web Services. Operating systems and runtimes include ports and efforts involving Linux kernel, FreeBSD, NetBSD, OpenBSD, Zephyr Project, RT-Thread, Android (operating system), Docker, Kubernetes, Apache Software Foundation projects, and language runtimes for Golang, Rust (programming language), Python (programming language), Java (programming language), and LLVM-based toolchains. Academic courses, workshops, and training have been organized at institutions such as Massachusetts Institute of Technology, Carnegie Mellon University, Imperial College London, University of Toronto, and firms including ARM Ltd. and Intel Corporation.

Performance and Benchmarks

Performance studies and benchmark suites have been reported using benchmarks and frameworks maintained by SPEC, EEMBC, CoreMark, Dhrystone, LINPACK, SPECrate, Rodinia, PARSEC (benchmark suite), and custom workloads developed in collaborations with Stanford University, Berkeley Lab, Argonne National Laboratory, Los Alamos National Laboratory, CERN, and industrial partners such as NVIDIA and Intel. Comparative analyses often reference microarchitectures and commercial products from ARM Holdings, Intel Corporation, AMD, MIPS Technologies, Sun Microsystems, and custom research cores developed at IBM Research and in EU projects funded by Horizon 2020. Metrics reported include IPC, throughput, energy per instruction, and performance per watt measured on silicon from foundries like TSMC and evaluated in labs equipped with instrumentation from Keysight Technologies and Tektronix.

Industry Adoption and Governance

Governance, ecosystem coordination, and industry advocacy involve entities such as RISC-V International, consortia with members including SiFive, Western Digital, NVIDIA, Google (company), Samsung Electronics, Alibaba Group, Qualcomm, Intel, IBM, Andes Technology, SiLabs, Microchip Technology, Xilinx, Cadence Design Systems, Synopsys, Mentor Graphics, EDA Consortium, and academic partners including University of California, Berkeley and ETH Zurich. Adoption has prompted policy discussions and procurement considerations in jurisdictions including United States, European Union, China, India, and Japan, and has intersected with standards dialogues involving ISO, IEC, IEEE Standards Association, and industrial alliances such as Open Compute Project and Linux Foundation initiatives. Licensing, intellectual property, export control, and certification efforts have engaged legal and standards groups tied to World Trade Organization, national ministries of commerce, and national laboratories including Sandia National Laboratories and Lawrence Berkeley National Laboratory.

Category:Instruction set architectures