Moore’s Law Consortium

Moore’s Law Consortium
Name	Moore’s Law Consortium
Formation	2010s
Type	Research consortium
Headquarters	Silicon Valley
Region served	Global
Leader title	Director

Moore’s Law Consortium

The Moore’s Law Consortium is a collaborative research alliance formed to extend the scaling trajectory associated with Gordon Moore, Intel, semiconductor manufacturing, and integrated circuit design through cooperative research, shared facilities, and cross-institutional funding. It brings together academic institutions, national laboratories, corporate research divisions, and standards bodies to pursue innovations in lithography, materials science, device physics, computer architecture, and nanotechnology. The Consortium coordinates efforts among stakeholders in Silicon Valley, Cambridge (UK), Tsukuba, and other technology hubs to sustain performance gains traditionally predicted by Moore's law.

History

The Consortium emerged in the 2010s amid concerns raised by researchers at Intel, IBM, TSMC, Samsung Electronics, and GlobalFoundries about slowing node scaling and rising costs for extreme ultraviolet lithography, finite element analysis, and quantum tunnelling mitigation. Early meetings included representatives from Stanford University, Massachusetts Institute of Technology, University of California, Berkeley, Lawrence Berkeley National Laboratory, and ETH Zurich, and drew on precedents set by consortia such as SEMATECH, IMEC, and CERN. Initial projects built on breakthroughs reported in journals like Nature Electronics, IEEE Transactions on Electron Devices, and Applied Physics Letters, and coordinated with standards work at JEDEC, ISO, and IEC.

Mission and Objectives

The Consortium’s mission emphasizes extending device density, energy efficiency, and manufacturability across successive process nodes while addressing thermal and reliability limits identified by teams at Bell Labs, DARPA, NIST, and Riken. Objectives include advancing extreme ultraviolet lithography adoption championed by ASML, developing alternative channel materials inspired by Graphene and transition metal dichalcogenide research, improving interconnect solutions referencing work from IEEE, and promoting open testbeds similar to initiatives at Fermilab and SLAC National Accelerator Laboratory.

Membership and Governance

Membership comprises corporate members from Intel Corporation, NVIDIA, Qualcomm, Broadcom, and Apple Inc., research members from Carnegie Mellon University, University of Illinois Urbana–Champaign, University of Tokyo, and national labs including Oak Ridge National Laboratory and Argonne National Laboratory, and partner organizations such as SEMATECH and IMEC. Governance uses a board model with representatives from industry, academia, and labs mirroring structures at The National Science Foundation consortia, and appoints technical committees akin to IETF working groups. Leadership roles include a Director, Technical Chair, and Finance Committee drawn from participating institutions like Harvard University and California Institute of Technology.

Research and Development Initiatives

R&D initiatives span device research on FinFET alternatives and gate-all-around transistor architectures, interconnect research referencing copper interconnect scaling and low-k dielectric advances, and packaging efforts inspired by 3D stacking and chiplet ecosystems championed by AMD. Projects investigate novel materials such as silicon-germanium, III-V semiconductors, graphene, and molybdenum disulfide leveraging techniques developed at Max Planck Institute for Solid State Research and Riken Center for Advanced Photonics. Collaborative work addresses metrology improvements from SEMATECH and NIST test protocols, and software-hardware co-design drawing on methods from DARPA programs and Open Compute Project philosophies.

Partnerships and Industry Impact

Partnerships include foundry collaborations with TSMC and Samsung, equipment partnerships with ASML, Tokyo Electron, and Applied Materials, and academic collaborations with ETH Zurich, University of Cambridge, and Peking University. The Consortium influences roadmaps at IC Insights, shapes standards with JEDEC and ISO, and informs procurement and capital planning at major fabs such as GlobalFoundries and SMIC. Its outputs affect supply-chain decisions involving Micron Technology, SK Hynix, and KLA Corporation, and downstream design practices at ARM Holdings, Cadence Design Systems, and Synopsys.

Funding and Resource Allocation

Funding combines membership dues from corporations like Intel Corporation and NVIDIA, grants from agencies including DARPA, NSF, European Research Council, and in-kind contributions of equipment from ASML and Applied Materials. Resource allocation follows peer-reviewed proposals evaluated by panels with expertise from IEEE, ACM, and national labs, and prioritizes shared cleanroom time, prototype foundry runs at multi-project wafer programs, and access to metrology tools at facilities like Lawrence Livermore National Laboratory.

Criticisms and Future Directions

Critics cite potential conflicts of interest involving dominant members such as Intel and TSMC, intellectual property allocation disputes similar to controversies at SEMATECH, and concerns about consolidation mirrored in debates about antitrust and market power in the microelectronics sector. Future directions include exploring quantum computing device interfaces studied at IBM Research and Google Quantum AI, advancing heterogeneous integration inspired by 3D XPoint research, and coordinating international resilience planning in response to supply-chain shocks like those affecting Taiwan Semiconductor Manufacturing Company and global shortages noted during the COVID-19 pandemic. Ongoing governance reforms reference models from CERN and The National Academies to balance openness, competition, and long-term research goals.

Category:Technology consortia Category:Semiconductor industry