Generated by GPT-5-mini| IEEE Electron Device Letters | |
|---|---|
| Title | IEEE Electron Device Letters |
| Discipline | Electronics, Semiconductor devices |
| Abbreviation | IEEE Electron Device Lett. |
| Editor | (see Editorial board and peer review) |
| Publisher | IEEE |
| Country | United States |
| History | 1980–present |
| Frequency | Monthly |
| Openaccess | Hybrid |
| Issn | 0741-3106 |
IEEE Electron Device Letters
IEEE Electron Device Letters is a peer-reviewed scientific journal publishing short reports on semiconductor transistor design, integrated circuit components, and nanoscale device physics. The journal serves as a rapid-communication venue linking research from laboratories at institutions such as Bell Labs, Stanford University, Massachusetts Institute of Technology, and Tsinghua University with developments at industrial organizations like Intel, Samsung Electronics, and TSMC. It is published by Institute of Electrical and Electronics Engineers and is associated with the community of researchers who also publish in venues such as IEEE Transactions on Electron Devices, Applied Physics Letters, Nature Nanotechnology, and IEEE Journal of Solid-State Circuits.
Founded in 1980 during a period of vigorous expansion in semiconductor research and the rise of very-large-scale integration, the journal emerged alongside contemporaries like Solid-State Electronics and Journal of Applied Physics. Early editorial direction reflected priorities of laboratories at AT&T Bell Laboratories, Hewlett-Packard, and IBM Research as they pursued scaling roadmaps articulated at conferences such as the International Electron Devices Meeting and the Device Research Conference. Through the 1980s and 1990s it tracked transitions from MOSFET scaling to novel architectures explored at University of California, Berkeley, University of Illinois Urbana-Champaign, and Cornell University, while later decades incorporated work on graphene from groups at University of Manchester and Columbia University and on FinFET developments at industrial centers including GlobalFoundries.
The journal emphasizes concise reports on device physics, novel transistor structures, low-dimensional materials, and fabrication techniques developed at facilities such as Sandia National Laboratories, Argonne National Laboratory, and National Institute of Standards and Technology. Topics commonly intersect with research produced for conferences like the IEEE International Electron Devices Meeting, the Materials Research Society meetings, and the International Conference on Solid State Devices and Materials, and draw authors from departments at California Institute of Technology, University of Tokyo, Imperial College London, and ETH Zurich. Content includes experimental measurements, simulation studies, and proposals for circuit integration relevant to companies such as Micron Technology and Texas Instruments.
Articles are indexed in major databases including Science Citation Index Expanded, Scopus, and INSPEC, alongside aggregation by services like Google Scholar and Web of Science. Citations connect the journal to landmark publications in Physical Review Letters, Nature Electronics, and IEEE Transactions on Nanotechnology, enabling cross-referencing with work by researchers from institutions such as Princeton University, Yale University, and Seoul National University.
The editorial board has historically drawn editors and associate editors from leading academic and corporate research groups, including faculty from Peking University, National University of Singapore, Delft University of Technology, and researchers from NVIDIA Research and ARM Holdings. Peer review follows standards common to journals like IEEE Transactions on Electron Devices and Applied Physics Letters, relying on anonymous reviewers from peer institutions such as Rensselaer Polytechnic Institute, University of Cambridge, and Osaka University to assess novelty and experimental rigor. Guest editors have coordinated special sections tied to symposia at IEEE flagship conferences and initiatives affiliated with awards like the IEEE Medal of Honor and the IEEE David Sarnoff Award.
Published on a monthly schedule, the journal issues short-format letters that prioritize rapid dissemination similar to formats used by Letters in Applied Microbiology and Physical Review Letters. Articles are typically 2–4 pages, including figures and tables, and are available in print and online through the IEEE Xplore Digital Library. Special issues have coincided with proceedings from events such as the International Symposium on VLSI Technology and collections highlighting breakthroughs from research centers like IMEC.
The journal is regarded as a venue for fast, targeted communication of device innovations and is cited alongside influential outlets like IEEE Transactions on Electron Devices and Nature Communications in literature reviews produced by groups at Lawrence Berkeley National Laboratory, CERN-affiliated projects on detector electronics, and corporate R&D teams at Qualcomm. Its impact factor and citation metrics place it within the competitive cohort of applied physics and electronic engineering journals, and it has been referenced in patent literature from firms such as STMicroelectronics and Analog Devices.
Notable contributions include early reports on scaled MOSFET performance from researchers at Bell Labs and IBM Research, demonstrations of novel two-dimensional material devices from teams at University of Manchester and Columbia University, and rapid disclosures of architecture adjustments later adopted by foundries like TSMC and Samsung. Papers have influenced subsequent reviews in Annual Review of Materials Research and guided technology roadmaps discussed at International Technology Roadmap for Semiconductors workshops and strategic planning at institutions including DARPA and National Science Foundation.
Category:IEEE journals Category:Electronics journals