Quartus Prime

Quartus Prime. It is a comprehensive software suite for field-programmable gate array design and development, created and maintained by Intel Corporation. The platform integrates a complete environment for system design, synthesis, placement, routing, verification, and programming, primarily targeting Intel's portfolio of programmable logic devices. It succeeds the widely used Quartus II software, introducing enhanced performance, a modernized user interface, and support for advanced device architectures.

Overview

The software provides a unified workflow for designing complex digital systems, from initial hardware description language entry to final device configuration. It is integral to developing applications for sectors like data center acceleration, 5G networks, and industrial automation. The environment is deeply integrated with other Intel tools, such as the Intel HLS Compiler and DSP Builder, enabling high-level system design. Engineers utilize its capabilities to implement everything from simple glue logic to sophisticated system-on-a-chip prototypes on programmable hardware.

Features

Key capabilities include advanced timing analysis through the TimeQuest Timing Analyzer and powerful logic synthesis engines. The Platform Designer tool facilitates rapid integration of intellectual property cores and custom logic into system-on-a-chip architectures. For debugging, the SignalTap II Logic Analyzer allows real-time inspection of internal node signals without requiring external hardware. The software also supports OpenCL and high-level synthesis flows, enabling software developers to target FPGA platforms. Integration with version control systems like Git and scripting via Tcl commands supports complex project management and automation.

Editions

The software is offered in several tiers to cater to different design needs. The **Standard Edition** provides core design capabilities for mainstream Intel FPGA families like Cyclone and MAX. The **Pro Edition** adds advanced features, including support for the high-performance Intel Stratix series and faster compilation times. The **Lite Edition** is a free version with limited device support, ideal for educational purposes and small designs. Subscription licenses are managed through the Intel FPGA Software Installer and provide access to regular updates and patches.

Supported Devices

The toolchain supports the full spectrum of Intel programmable logic, from low-cost, low-power families to high-bandwidth, high-performance devices. This includes the entire Intel Agilex product line, the Intel Stratix series, the cost-optimized Intel Cyclone family, and the non-volatile Intel MAX series. Support also extends to legacy device families originally developed by Altera, such as Arria and the classic Stratix devices, ensuring design migration paths. Compatibility with various configuration devices, like the EPCQ and EPCS serial flash memory, is also included.

Design Flow

A typical project begins with design entry using VHDL, Verilog, or SystemVerilog, or via schematic capture. The design is then processed through synthesis, mapping, placement, and routing stages, culminating in the generation of a programming file. Critical analysis steps, including power estimation with the PowerPlay Power Analyzer and formal verification, are performed throughout. The final SRAM Object File or Programmer Object File is loaded onto the target device using the integrated programmer or tools like the USB-Blaster download cable. This flow is managed within the Quartus Prime GUI or can be fully driven by command-line scripts.

History

The software was launched in 2015 as the successor to Quartus II, which had been the flagship EDA tool for Altera Corporation since 2000. Its development accelerated following the acquisition of Altera by Intel in a deal valued at approximately US$16.7 billion. Subsequent releases have focused on supporting new architectures like Intel Agilex, improving compilation speed, and enhancing integration with the broader Intel software ecosystem, including the oneAPI initiative. Major version updates align with the introduction of new device families and significant feature enhancements.