Verilog

Verilog. It is a hardware description language used to model electronic systems, most commonly digital circuits. Originally created by Phil Moorby at Gateway Design Automation in the mid-1980s, it became a cornerstone of electronic design automation. The language is standardized as IEEE 1364 and is widely used for design verification and logic synthesis in the semiconductor industry.

History

The language was invented in 1983-1984 by Phil Moorby while working at Gateway Design Automation, a company later acquired by Cadence Design Systems. Its initial purpose was for logic simulation of application-specific integrated circuits. The proprietary language gained rapid adoption, leading to its transfer to the public domain in 1990. This move was overseen by Open Verilog International, a consortium that drove its standardization. The first official standard, IEEE 1364-1995, was ratified by the Institute of Electrical and Electronics Engineers, cementing its role alongside VHDL. Subsequent revisions, including IEEE 1364-2001 and IEEE 1364-2005, introduced significant enhancements.

Language Features

The syntax is heavily influenced by the C (programming language), making it accessible to software engineers. Its core modeling constructs operate at various levels of abstraction, including gate-level modeling and behavioral modeling. Key elements include modules as design blocks, nets and registers for data storage and connectivity, and always blocks for describing sequential logic. It supports explicit concurrency to model parallel hardware operations and uses an event-driven simulation algorithm. User-defined primitives allow for custom gate-level modeling, while testbench constructs facilitate design verification.

Design Methodology

It enables a top-down design methodology, allowing engineers to describe system functionality at a high register-transfer level before refining it into a gate-level netlist. This flow is central to modern electronic design automation tools from vendors like Synopsys and Cadence Design Systems. A typical design process involves creating RTL design descriptions, which are then verified using simulation against a testbench. The design under test is stimulated with various test vectors to ensure correctness before logic synthesis transforms the register-transfer level code into a technology-specific implementation. This methodology is critical for designing complex integrated circuits like those from Intel or Advanced Micro Devices.

Simulation and Synthesis

Logic simulation is a primary use case, with events scheduled on a discrete-event simulation timeline managed by a Verilog simulator such as ModelSim or VCS (simulator). The simulation kernel processes blocking assignments and non-blocking assignments to accurately model hardware timing. For logic synthesis, a subset of the language, known as the synthesizable subset, is used by tools like Design Compiler from Synopsys to convert RTL design into a gate-level netlist of standard cells from a technology library. The distinction between simulation semantics and synthesis semantics is crucial, as not all constructs used for testbench creation can be realized in physical silicon.

Related Languages and Standards

Its direct evolutionary successor is SystemVerilog, developed by Accellera and standardized as IEEE 1800, which adds extensive verification and design capabilities. The main historical rival is VHDL, developed under contract for the United States Department of Defense and standardized as IEEE 1076. Other related hardware description languages include Chisel and SpinalHDL. The broader ecosystem includes standards like SystemC for system-level design and the Universal Verification Methodology built on top of SystemVerilog. Ongoing development is managed by Accellera and the Institute of Electrical and Electronics Engineers. Category:Hardware description languages Category:IEEE standards Category:Electronic design automation