VHDL

VHDL. VHDL is a hardware description language used in electronic design automation to model and design digital and mixed-signal systems. It was originally developed under contract for the United States Department of Defense and has since become a cornerstone of integrated circuit and field-programmable gate array design. The language enables the description of a system's structure and behavior, facilitating simulation, synthesis, and verification before physical implementation.

History and development

The language's creation was initiated in the early 1980s by the United States Department of Defense through its VHSIC program, which aimed to advance integrated circuit technology. The initial requirements were drafted by a team of contractors, including IBM, Texas Instruments, and Intermetrics, with the goal of documenting the behavior of ASICs supplied to the military. The first publicly available version, standardized as IEEE 1076-1987, was ratified by the Institute of Electrical and Electronics Engineers in 1987. Subsequent revisions, such as IEEE 1076-1993 and IEEE 1076-2008, introduced significant enhancements, including improved synthesis capabilities and support for protected shared variables. The language's evolution has been closely tied to the parallel development of Verilog, its main rival, and the standardization efforts of the Accellera organization.

Language features and syntax

VHDL is a strongly typed, case-insensitive language with syntax and semantics heavily influenced by the Ada programming language. Its core modeling constructs are based on a discrete event simulation paradigm, where designs are expressed using entities, architectures, processes, and signals. Key features include support for concurrent and sequential statements, a rich set of data types like std_logic defined in the IEEE 1164 standard, and packages for code modularity. The language provides extensive capabilities for describing register-transfer level logic, finite-state machines, and testbenches, utilizing features such as generics for parameterization and configurations for design management. Its design units are compiled into libraries, promoting a structured, hierarchical approach to complex system design.

Design methodology and applications

VHDL is fundamental to modern electronic design automation workflows, particularly in the design and verification of digital electronics. It is extensively used for register-transfer level modeling, which serves as the input for logic synthesis tools that generate gate-level netlists for ASICs and FPGAs. Major EDA vendors like Synopsys, Cadence Design Systems, and Mentor Graphics (now part of Siemens) provide comprehensive toolchains supporting the language. Applications span from designing microprocessors, such as those from Intel and ARM, to creating complex communication systems and aerospace avionics. The language also plays a critical role in verification methodologies, often integrated with frameworks like the Universal Verification Methodology to ensure design correctness.

Simulation and synthesis

Simulation is a primary use case, allowing designers to execute models and verify functionality against specifications using testbenches before fabrication. Commercial simulators from companies like Cadence Design Systems (Incisive) and Synopsys (VCS) are industry standards. Synthesis, the process of transforming a register-transfer level description into a gate-level implementation, is supported by tools such as Synopsys Design Compiler and Xilinx Vivado. The distinction between code intended for simulation and code suitable for synthesis is a critical aspect of design practice; constructs like `wait for` statements are simulatable but not synthesizable. Standards like IEEE 1076.6 provide guidelines for synthesis subset compliance, ensuring portability across different foundries and FPGA vendors.

Standards and related languages

The language is governed by the IEEE 1076 standard, maintained by the Institute of Electrical and Electronics Engineers. Important auxiliary standards include IEEE 1164 for multivalue logic systems and IEEE 1076.3 for numeric packages. Its main competitor is Verilog, which led to the creation of the unified SystemVerilog standard overseen by Accellera. Other related hardware description and modeling languages include SystemC, which is often used for transaction-level modeling, and MyHDL, a Python-based alternative. The language continues to evolve, with recent revisions incorporating features from modern programming languages to better support verification and design reuse methodologies prevalent in the semiconductor industry.

Category:Hardware description languages Category:IEEE standards Category:Programming languages created in the 1980s