Stratix

Stratix. Stratix is a family of high-performance, high-density field-programmable gate array (FPGA) devices originally developed by Altera Corporation and now produced by Intel Corporation following its acquisition. First introduced in 2002, the Stratix series was designed to address the demanding needs of high-bandwidth applications in sectors such as telecommunications, military technology, and broadcasting. It succeeded the APEX 20K architecture and has since evolved through multiple generations, incorporating advanced features like embedded microprocessor cores, high-speed serial transceivers, and hardened intellectual property blocks. The family represents a cornerstone in the evolution of programmable logic, enabling rapid prototyping and system integration for complex digital designs.

Overview

The Stratix architecture emerged during a period of intense competition in the programmable logic market, primarily against Xilinx's Virtex series. Its introduction marked a significant leap in logic density and performance, leveraging a 0.13 µm CMOS process technology from foundry partner TSMC. Key innovations included a hierarchical routing structure and the integration of dedicated digital signal processing (DSP) blocks, which were critical for computationally intensive tasks like those found in wireless communication base stations. The devices also featured enhanced memory resources with both triple-speed Ethernet support and double data rate (DDR) SDRAM controllers, facilitating their adoption in data center and network processor applications. Over successive generations, Stratix FPGAs incorporated hardened blocks for Peripheral Component Interconnect Express (PCIe) and Gigabit Ethernet, reducing power consumption and latency compared to soft IP implementations.

Architecture

At its core, the Stratix architecture employs a logic array block (LAB) and adaptive logic module (ALM) structure, providing a flexible fabric for implementing complex combinational and sequential logic. Each device contains an array of these programmable elements interconnected by a multi-level routing hierarchy of local, regional, and global networks. Dedicated high-performance blocks are interspersed throughout the fabric, including the MegaLAB structure, M-RAM memory blocks, and the DSP Block for fixed-point and floating-point arithmetic operations. Advanced I/O capabilities support a wide range of standards such as LVDS, SSTL, and HSTL, enabling direct interfacing with microprocessors like the PowerPC and ARM-based systems. Later generations, such as Stratix V, integrated 28 Gbps transceivers and hardened IEEE 754-compliant floating-point units, targeting applications in high-performance computing and radar systems.

Product Families

The Stratix lineage comprises several distinct families, each advancing process technology and feature integration. The original Stratix GX series, introduced in 2003, was among the first to include multi-gigabit serial transceivers for SONET and Serial ATA protocols. This was followed by Stratix II and Stratix II GX, which utilized a 90 nm process and introduced the ALM for improved logic efficiency. Stratix III and Stratix IV families migrated to 65 nm and 40 nm processes, respectively, offering enhanced DSP Block performance and support for DDR3 SDRAM. The Stratix V series, built on a 28 nm HKMG process, featured integrated hard PCI Express Gen3 blocks and advanced transceivers. The final Altera-branded generation, Stratix 10, leverages Intel's 14 nm FinFET technology and incorporates heterogeneous system-in-package (SiP) designs with ARM Cortex-A53 cores, preceding the current Intel Agilex platform.

Development Tools

Design and implementation for Stratix devices are primarily conducted using Intel Quartus Prime, the flagship electronic design automation (EDA) software suite inherited from Altera. This integrated environment provides a complete flow from register-transfer level (RTL) design entry and logic synthesis using Synopsys synthesis technology, to place and route optimization, timing analysis, and in-system programming. The software includes the Platform Designer (formerly Qsys) system integration tool for connecting intellectual property cores and the Nios II embedded processor. Support for high-level synthesis is available through tools like Intel HLS Compiler, allowing design entry in C++ and OpenCL. Third-party EDA tools from Mentor Graphics and Cadence Design Systems are also supported for simulation and formal verification, facilitating integration into broader ASIC design flows.

Applications

Stratix FPGAs are deployed in a vast array of high-end, compute-intensive applications where flexibility, performance, and time-to-market are critical. In the telecommunications sector, they are used for 4G and 5G baseband processing, network function virtualization (NFV), and optical transport network (OTN) switching. Within defense electronics, they serve as the processing heart for synthetic aperture radar (SAR), electronic warfare suites, and image processing in unmanned aerial vehicles (UAVs). The broadcast industry utilizes them for real-time video compression standards like JPEG 2000 and Ultra HD video processing. Furthermore, in financial technology, Stratix devices accelerate algorithmic trading and risk modeling, while in medical imaging, they enable rapid reconstruction in computed tomography (CT) and magnetic resonance imaging (MRI) machines.

Category:Field-programmable gate arrays Category:Intel products Category:Altera