Gate-all-around

Gate-all-around
Name	Gate-all-around
Type	Transistor architecture
Introduced	2010s
Designer	Intel Corporation, Samsung Electronics, TSMC
Used in	Central processing unit, System on a chip, Mobile device

Gate-all-around

Gate-all-around is a transistor architecture that surrounds a semiconducting channel with a gate electrode on all sides to improve electrostatic control. Developed as a successor to FinFET designs, it has been pursued by Intel Corporation, Samsung Electronics, and TSMC to extend Moore's Law and enable continued scaling for Central processing units, System on a chips, and high-performance logic. The architecture has driven research across University of California, Berkeley, Massachusetts Institute of Technology, IMEC, and industrial fab ecosystems.

Overview

Gate-all-around offers a three-dimensional device geometry in which the gate electrode encircles the active channel to suppress short-channel effects noted in the later nodes of Intel Corporation and Samsung Electronics roadmaps. The technology emerged as part of multi-company roadmaps alongside developments from TSMC and research centers such as IMEC and GlobalFoundries. Early experimental demonstrations involved collaborations among University of California, Berkeley, Massachusetts Institute of Technology, and Tokyo Institute of Technology laboratories, while commercialization timelines were announced by Intel Corporation for logic processes and by Samsung Electronics for mobile logic. Gate-all-around aims to replace or complement FinFET and to interact with lithography innovations from ASML and materials advances from BASF and Dow Chemical Company.

Device Structure and Operation

The device typically uses vertical or horizontal channel geometries formed as either nanowires or nanosheets produced by patterning and etch sequences used in fabs operated by TSMC and Intel Corporation. In nanosheet implementations the gate, gate dielectric, and workfunction material wrap the channel fully, improving threshold voltage control used in Central processing unit designs by Advanced Micro Devices and Nvidia. Gate-all-around devices rely on atomic-layer deposition processes from suppliers like Lam Research and Applied Materials and incorporate high-κ dielectrics developed by Intel Corporation and Samsung Electronics research groups. The operational physics draws on quantum confinement and electrostatic gating concepts explored at University of Cambridge and Eindhoven University of Technology.

Fabrication and Materials

Fabrication leverages multi-patterning lithography from ASML immersion and extreme ultraviolet tools, etch tools from Lam Research and Tokyo Electron Limited, and epitaxial growth techniques common at GlobalFoundries and UMC. Channel materials include silicon, silicon-germanium alloys used historically by IBM research, and proposals for III-V semiconductors evaluated by IMEC and Intel Corporation to enhance mobility. Gate stacks use high-κ materials and metal gates pioneered in projects involving Samsung Electronics, Intel Corporation, and TSMC. Integration also uses chemical mechanical planarization and metrology tools from KLA Corporation and Onto Innovation; backend processes draw on packaging partners such as ASE Technology Holding and Amkor Technology.

Performance and Scaling Advantages

Gate-all-around provides superior electrostatic control compared with planar MOSFETs and FinFETs, enabling lower off-state leakage and better subthreshold slope reported in device studies by Intel Corporation and Samsung Electronics. The architecture supports multiple nanosheet widths to tune drive current, a feature highlighted by TSMC in node roadmaps for Central processing unit and Graphics processing unit products by Nvidia and Advanced Micro Devices. Improved short-channel suppression aids continued scaling to sub-5 nm nodes targeted by Intel Corporation and TSMC while interfacing with extreme ultraviolet lithography advances from ASML and packaging trends driven by Intel Corporation and Apple Inc..

Challenges and Reliability

Manufacturing complexity raises yield and variability concerns that fabs at TSMC and Samsung Electronics address through process control frameworks developed with equipment suppliers like Applied Materials and Lam Research. Reliability issues include bias temperature instability, hot-carrier effects, and variability tied to interface states studied at IMEC and Bell Labs. Thermal management in dense logic blocks affects designs by Intel Corporation and Apple Inc.; electromigration and interconnect resistance challenges relate to materials choices from Nippon Steel and Copper Development Association. Design-for-manufacturability efforts by Cadence Design Systems and Synopsys integrate new cell libraries and models to mitigate variability in System on a chip implementations.

Applications and Industry Adoption

Gate-all-around has been adopted in leading-edge logic by Samsung Electronics and preceded commercialization plans by Intel Corporation and TSMC for mobile, server, and high-performance computing markets, influencing products from Apple Inc., Nvidia, and Advanced Micro Devices. Research into low-power microcontrollers and IoT devices involves partners like STMicroelectronics and NXP Semiconductors, while academic and government labs including Lawrence Berkeley National Laboratory and DARPA have funded exploratory materials and device studies. The architecture figures into supply-chain strategies across fabs, equipment vendors, and design companies such as Qualcomm and Broadcom as part of continued scaling and heterogeneous integration initiatives.

Category:Semiconductor devices