Central processing unit

Central processing unit
Name	Central processing unit
Invented	1940s
Designer	Various
Manufacturer	Various
Introduced	1940s
Architecture	Various

Central processing unit is the primary electronic circuit that executes instructions comprising computer programs, coordinating arithmetic, logic, control, and input/output operations. It evolved from vacuum-tube calculators to modern microprocessors used in desktops, servers, mobile devices, and embedded systems. Developments in transistor scaling, instruction set design, and fabrication have driven wide variations in performance, power, and integration across computing platforms.

History

Early development involved pioneers and projects such as Alan Turing's theoretical work, the ENIAC team, and the Manchester Baby. Postwar milestones include the EDVAC concept and the von Neumann architecture debated by John von Neumann and contemporaries. The transition from vacuum tubes to transistors at Bell Labs and the invention of the integrated circuit credited to Jack Kilby and Robert Noyce enabled commercial processors like the Intel 4004 and the Motorola 6800 families. The microprocessor revolution fostered companies such as Intel, AMD, ARM Holdings, and IBM, while competition and standards efforts involved organizations like MIPS Technologies and the OpenPOWER Foundation. Key historical products and events include the IBM System/360 series, the rise of personal computing with the Apple II and Commodore 64, and the client–server era accelerated by Intel Pentium and AMD Athlon lines. Later shifts to mobile and heterogeneous computing saw the influence of ARM architecture, the emergence of NVIDIA GPUs for acceleration, and collaborations such as Apple Inc.'s in-house silicon initiatives.

Architecture and Components

A CPU's organization typically separates datapath, control unit, and registers; implementations range from simple accumulator machines to complex superscalar designs. Classic components include the arithmetic logic unit (ALU), floating-point unit (FPU), integer register file, program counter, instruction decoder, and condition code registers. Microarchitectural elements appear as pipelines, reorder buffers, branch predictors, and cache hierarchies often influenced by research from institutions like MIT, Stanford University, and University of California, Berkeley. Memory subsystem interactions reference primary memory controllers, level 1/2/3 caches, and coherence protocols used in multiprocessor systems exemplified by SMP deployments in Sun Microsystems and SGI servers. System-level interfaces include buses and interconnects such as PCI Express, DDR SDRAM controllers, and fabrics like InfiniBand in high-performance computing clusters.

Instruction Set and Microarchitecture

Instruction set architectures (ISAs) define programmer-visible operations, with prominent ISAs including those from Intel (x86), ARM Holdings (ARM), MIPS Technologies (MIPS), and open efforts such as RISC-V. ISA choice influences compiler ecosystems (e.g., GCC, LLVM) and operating system support in projects like Windows NT, Linux kernel, and macOS. Microarchitecture implements an ISA through pipelines, out-of-order execution, speculative execution, and micro-op translation; famous implementations reflect designs from Intel's Core series, AMD's Zen series, and research prototypes from Bell Labs and university labs. Security research following disclosures like the Meltdown and Spectre vulnerabilities prompted architectural mitigations and microcode updates coordinated with vendors such as Microsoft and Google.

Performance and Benchmarking

CPU performance metrics include instructions per cycle (IPC), clock frequency, throughput, latency, and energy-per-instruction; benchmarking suites from organizations and projects like SPEC and EEMBC provide comparative measures. Real-world workloads reference databases such as TPC-C for transaction processing, scientific codes from NASA and CERN, and multimedia workloads influenced by codecs standardized by bodies like MPEG. Supercomputing rankings in the TOP500 rely on CPU and accelerator performance; vendors such as Cray (now part of HPE), Fujitsu, and NVIDIA shape performance through system integration. Compiler optimizations, microarchitectural tuning, and parallelization frameworks like OpenMP and MPI further affect benchmark outcomes.

Manufacturing and Packaging

Fabrication uses silicon CMOS processes optimized by foundries including Intel, TSMC, Samsung Electronics, and GlobalFoundries. Process nodes historically tracked by feature sizes (e.g., 14 nm, 7 nm, 5 nm) reflect lithography advances and collaborations with equipment suppliers like ASML (extreme ultraviolet lithography). Die packaging ranges from monolithic chips to multi-chip modules and chiplet approaches adopted by AMD and others, using substrate technologies and interposers from suppliers such as Amkor Technology and ASE Technology. Yield, defect density, and design-for-manufacturability practices determine unit cost and market positioning in products from vendors like Dell Technologies and Lenovo.

Cooling, Power Consumption, and Reliability

Thermal management spans passive heat sinks, active fans, liquid cooling loops, and data-center solutions from Schneider Electric and Vertiv. Power management features include dynamic voltage and frequency scaling (DVFS) implemented in coordination with firmware standards like ACPI and power monitoring from servers in Amazon Web Services and Microsoft Azure datacenters. Reliability engineering addresses soft errors, error-correcting code (ECC) memory, fault-tolerant designs used in aerospace projects by Lockheed Martin and NASA, and lifetime wear-out mechanisms characterized during qualification by industry consortia such as JEDEC.

Applications and System Integration

CPUs are integrated into systems ranging from embedded controllers in Siemens industrial automation to consumer platforms from Sony and Nintendo, enterprise servers by Oracle Corporation and Hewlett Packard Enterprise, and scientific clusters at institutions like Lawrence Livermore National Laboratory. Heterogeneous systems combine CPUs with GPUs from NVIDIA, FPGAs from Xilinx (now part of AMD), and dedicated accelerators for AI developed by Google (TPU) or startups such as Graphcore. Software ecosystems—compilers, operating systems, virtualization stacks like VMware and container platforms such as Docker—mediate CPU resources across applications in cloud, edge, and embedded deployments.

Category:Computer hardware