Peripheral Component Interconnect Express

Peripheral Component Interconnect Express
Name	Peripheral Component Interconnect Express
Caption	Logo for the standard
Invent-date	2003
Invent-name	PCI-SIG
Supersedes	PCI, AGP
Width	1–32
Num-devices	1 per slot
Speed	Varies per generation
Style	Serial
Hotplug	Yes (with specification)
External	Yes (as External PCIe)

Peripheral Component Interconnect Express. It is a high-speed serial computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus standards. Developed and maintained by the PCI-SIG, the consortium founded by Intel, IBM, Dell, Hewlett-Packard, and others, it is the dominant motherboard-level interconnect for connecting GPUs, SSDs, and other high-performance peripherals. Its point-to-point architecture, based on dedicated serial lanes, provides substantial performance and scalability advantages over the shared parallel bus of its predecessors.

Overview

The architecture fundamentally differs from previous standards by utilizing a dedicated, switched point-to-point topology rather than a shared parallel bus. This design, championed by engineers at Intel during its initial development under the codename "3GIO," eliminates bus contention and allows for much higher clock speeds. Each connection, known as a lane, consists of two differential signaling pairs for full-duplex communication. This standard is used to connect a vast array of internal components, from NVIDIA and AMD graphics cards to high-speed storage from Samsung and Western Digital, and has become ubiquitous in systems ranging from Apple MacBook laptops to Cray supercomputers.

Technical Specifications

Communication occurs via a layered protocol, comprising the Transaction Layer, Data Link Layer, and Physical Layer, analogous in concept to the OSI model. Data is packetized, with packets routed through the system based on memory addresses, I/O addresses, or configuration messages. Key enabling technologies include LVDS for the physical signaling and sophisticated clock data recovery circuits. Error detection and correction is handled by a CRC mechanism and an acknowledgment/retry protocol at the Data Link Layer, ensuring high data integrity. The electrical interface is defined for both internal motherboard connections and external cabling, as seen in specifications like the External PCIe.

Form Factors and Connectors

The standard defines several physical form factors to accommodate different space and bandwidth requirements. The most common is the PCIe slot found on motherboards, with physical lengths corresponding to lane counts (x1, x4, x8, x16). The M.2 form factor, which utilizes PCIe lanes, has become the standard for high-performance SSDs in laptops and desktops. For add-in cards, the PCI Express card specifications outline sizes like full-height and half-height. Other specialized connectors include U.2 (SFF-8639) for enterprise storage and the O Cu Link standard championed by the PCI-SIG for external GPU enclosures.

Generations and Performance

Performance has doubled approximately every generation, with each new version maintaining backward and forward compatibility at the connector level. The initial 1.0 specification, released in 2003, offered 2.5 GT/s per lane. This was followed by PCIe 2.0 in 2007, PCIe 3.0 in 2010, and PCIe 4.0 in 2017, the latter finalized after delays involving controller complexity from companies like AMD and Intel. PCIe 5.0 was released in 2019, and PCIe 6.0 was announced in 2021, introducing new technologies like PAM4 signaling. Each generation's increased bandwidth has been critical for supporting advancements in NVIDIA's GeForce series, AMD's Radeon cards, and the NVMe storage protocol.

Applications and Market Adoption

Its primary application is as the exclusive interface for discrete graphics cards, having completely supplanted AGP by the late 2000s. It is also the foundational bus for the NVMe protocol, which enables ultra-low-latency SSD storage, products of which are made by Intel, Samsung, and SK Hynix. In the data center, it forms the backbone of connectivity for SmartNICs from NVIDIA (Mellanox) and Intel, and is integral to high-speed interconnects like CXL and Gen-Z. Adoption is universal across all computing segments, from consumer devices like the Sony PlayStation 5 to high-performance computing systems at Oak Ridge National Laboratory.

Comparison with Other Bus Standards

Compared to its predecessor, the parallel PCI bus, it offers vastly superior bandwidth and scalability due to its serial, point-to-point design. It displaced the graphics-specific AGP by offering a more general-purpose, scalable pathway. For external connectivity, it competes with and often underpins standards like Thunderbolt (developed by Intel and Apple) and USB4, which can tunnel PCIe packets. Within the server and storage domain, it has largely replaced older parallel interfaces like Parallel ATA and SCSI, though specialized interconnects like InfiniBand and Ethernet remain dominant for specific cluster networking applications separate from internal expansion.

Category:Computer buses Category:Computer hardware standards Category:2003 introductions