PowerPC 603

PowerPC 603
Name	PowerPC 603
Caption	Die shot of the PowerPC 603
Produced	1994
Designer	IBM, Motorola
Manuf1	IBM
Manuf2	Motorola
Arch	PowerPC
Transistors	1.6 million
Process	0.5 µm
Predecessor	PowerPC 601
Successor	PowerPC 603e

PowerPC 603. The PowerPC 603 is a 32-bit microprocessor that implemented the PowerPC instruction set architecture. It was jointly developed by the AIM alliance partners IBM and Motorola as a low-power, cost-effective design primarily for portable and embedded systems. Introduced in 1994, it was a significant departure from its predecessor, the PowerPC 601, focusing on efficiency over raw performance for the emerging mobile computing market.

History

The development of the PowerPC 603 was driven by the strategic goals of the AIM alliance to expand the PowerPC architecture beyond high-performance workstations and into new markets. Following the introduction of the PowerPC 601 in 1993, engineers at IBM and Motorola sought to create a processor optimized for low power consumption and thermal output. This initiative was a direct response to the growing demand for processors in battery-powered laptop computers and various embedded system applications. The design team, drawing from expertise at the IBM Austin Research Laboratory and Motorola's Somerset design center, prioritized efficiency, leading to the chip's formal announcement in October 1994. Its release positioned it against contemporary x86 processors from Intel and AMD in the mobile segment, notably the Intel 80486 and early Pentium models.

Design

The PowerPC 603 employed a superscalar design capable of issuing up to three instructions per clock cycle to multiple independent execution units. Its microarchitecture featured a streamlined five-stage integer pipeline and a six-stage floating-point pipeline, a simplification compared to the more complex PowerPC 601. A key design philosophy was the implementation of a "power-on-demand" approach, where individual functional units could be selectively powered down when not in use. The chip utilized a Harvard architecture-style separate data and instruction caches, each 8 KB in size, connected via a 32-bit bus. This cache structure, along with its sophisticated branch prediction unit and support for both big-endian and little-endian data formats, was engineered to maximize performance per watt.

Features

A defining feature of the PowerPC 603 was its comprehensive power management system, which included software-controllable nap and sleep states to drastically reduce power consumption during idle periods. The processor fully implemented the 32-bit PowerPC instruction set, including the new user-level instructions defined in the architecture. It contained integrated memory management unit (MMU) hardware for virtual memory support. Other notable features included hardware support for both multiprocessing and multithreading configurations, although its primary use was in single-processor systems. The chip's fabrication initially used a 0.5 µm CMOS process technology, contributing to its relatively low thermal design power.

Performance

In performance benchmarks, the PowerPC 603 typically delivered lower integer and floating-point performance at a given clock speed compared to the PowerPC 601 and certainly the higher-end PowerPC 604. However, its performance was highly competitive within its intended low-power domain. Clock speeds at introduction ranged from 66 MHz to 80 MHz, with later variants reaching 100 MHz. Its performance per watt metric was exceptional for its time, making it attractive for portable applications where battery life was a critical concern. In direct comparisons with contemporary mobile x86 CPUs, it often showed strengths in RISC-typical workloads but could lag in legacy x86 code execution unless well-optimized by the operating system and applications.

Variants

The original PowerPC 603 was followed by an enhanced version, the PowerPC 603e, which increased the size of the caches to 16 KB each and improved the branch prediction logic. A derivative for the embedded market, the PowerPC 603r, offered additional features for real-time applications. Furthermore, IBM produced a radiation-hardened version, the RAD6000, for aerospace and satellite applications, based on the PowerPC 603 core. These variants extended the design's lifespan and applicability far beyond the original commercial computing goals. The core architecture also influenced later embedded processors within the PowerPC 7xx and PowerQUICC families from Motorola and later Freescale Semiconductor.

Applications

The PowerPC 603 found its most notable application in several early Power Macintosh models, such as the Power Macintosh 5200 LC and Power Macintosh 5300 LC, where its low heat output was advantageous for compact designs. It was also used in a number of PCI-based motherboards and evaluation boards for developers. Beyond Apple systems, it was adopted in various embedded systems, telecommunications equipment from companies like Cisco Systems, and in the automotive industry for engine control units. Perhaps its most long-lived application was in the aerospace sector, where the radiation-hardened RAD6000 variant served as the primary computer for numerous NASA missions, including the Mars Pathfinder and the Mars Exploration Rover missions.

Category:PowerPC microprocessors Category:IBM microprocessors Category:Motorola microprocessors Category:Computer-related introductions in 1994