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| RISC-V Rocket Core | |
|---|---|
| Name | Rocket Core |
| Designer | Berkeley Architecture Research |
| Architecture | RISC-V |
| Type | In-order scalar core |
| Release | 2010s |
| License | BSD |
RISC-V Rocket Core The RISC-V Rocket Core is an open-source, in-order scalar processor core developed as part of the Berkeley RISC-V project and implemented in Chisel (hardware description language). It served as a reference implementation for the RISC-V (ISA), influenced academic designs at the University of California, Berkeley and commercial projects at firms like SiFive and Western Digital. The Rocket Core catalyzed ecosystem growth across institutions such as ETH Zurich, Imperial College London, MIT, and companies including Google, NVIDIA, and Intel.
The Rocket Core emerged from the Berkeley Architecture Research group as a practical instantiation of the RISC-V base integer instruction set and optional extensions, designed to demonstrate principles promoted by the RISC movement and influenced by processors like the MIPS R2000 and the DEC Alpha. It is open-source under a permissive license enabling adoption by academic labs such as University of Cambridge Computer Laboratory and commercial entities including SiFive and Western Digital Corporation. The core was described in publications presented at venues such as the International Symposium on Computer Architecture, the Design Automation Conference, and the Symposium on High-Performance Computer Architecture.
Rocket implements the RV32 and RV64 base user-level architectures and supports optional extensions like the RISC-V compressed instruction set and the RISC-V atomic extension. Its pipeline is a classic five-stage in-order design influenced by textbooks used at UC Berkeley and Stanford University School of Engineering, with register file and branch units comparable in concept to structures from ARM Ltd. cores and the PowerPC 604. The core integrates a load–store unit compatible with coherence schemes used in multicore clusters from projects at Lawrence Berkeley National Laboratory and cache hierarchies similar to those in studies at Carnegie Mellon University and ETH Zurich. Interrupt and exception handling align with conventions described by committees like the RISC-V Foundation and standards discussed at IEEE conferences.
Rocket was written in Chisel (hardware description language), enabling parameterization and customization by groups such as SiFive, Western Digital, Antmicro, and research teams at Princeton University. Variants include larger configurations with branch prediction and out-of-order front-end experiments by labs at MIT CSAIL and Stanford University Computer Systems Laboratory. Implementations have been integrated into system-on-chip platforms alongside peripherals from vendors like ARM Holdings partners and FPGA deployments on platforms from Xilinx and Intel (Altera). Commercial derivatives powered products from SiFive used in collaborations with Google for edge accelerators and with Western Digital for storage controllers.
Performance studies for Rocket were published alongside comparisons to microarchitectures like the ARM Cortex-A53, MIPS32, and research cores such as OpenRISC. Benchmark suites used include workloads from the SPEC CPU family, the MiBench embedded suite, and academic workloads from PARSEC (benchmark suite) and the Benchmarks Game. Evaluations reported metrics such as IPC and energy per instruction in papers presented at the International Symposium on Low Power Electronics and Design and the International Conference on Computer-Aided Design, with measurements referenced by teams at Berkeley Lab and Sandia National Laboratories.
Toolchains and runtime support for Rocket are provided via projects at Free Software Foundation repositories and communities like the RISC-V Foundation ecosystem, integrating GNU toolchain ports maintained by contributors from Red Hat and Linaro. Operating systems ported include Linux kernel branches used by Yocto Project builds, real-time systems such as FreeRTOS, and academic OS work from UC Berkeley and Princeton University. Simulation and verification tools used in Rocket development include integrations with platforms from Cadence Design Systems, Synopsys, and open projects hosted by GitHub contributors from institutions like ETH Zurich and Imperial College London.
Rocket served as a research vehicle in projects across embedded systems labs at MIT, UC Berkeley and CMU, and in commercial use for prototyping controllers in products by SiFive and Western Digital. Its openness fostered deployment in academic demonstrators at events such as the Design Automation Conference and in collaborations on machine learning accelerators with teams from Google Brain and NVIDIA Research. Rocket-based designs were evaluated for use in edge devices by companies like Google and Amazon and in storage and data center controllers by Western Digital and Seagate Technology.
The Rocket Core was primarily developed by a team led within the Berkeley RISC-V project including notable contributors affiliated with the UC Berkeley EECS Department, with code contributions from engineers at SiFive and researchers collaborating from institutions like ETH Zurich, Imperial College London, MIT, and Princeton University. Early academic publications appeared at conferences such as the International Symposium on Computer Architecture and the Design Automation Conference, and the project received attention from industry participants including Google, NVIDIA, Intel, and Western Digital. The open-source releases catalyzed ecosystem projects at organizations like the RISC-V Foundation and spurred educational adoption at universities including Stanford University, Carnegie Mellon University, and the University of Cambridge.