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| Quartus Prime | |
|---|---|
| Name | Quartus Prime |
| Developer | Intel Corporation |
| Initial release | 2012 |
| Latest release | 2021 R2 (example) |
| Operating system | Microsoft Windows, Red Hat Enterprise Linux, CentOS |
| License | Proprietary software |
| Website | Intel FPGA product pages |
Quartus Prime is a proprietary integrated development environment produced by Intel Corporation for synthesis and analysis of hardware description languages targeting field-programmable gate arrays and complex programmable logic devices. It provides RTL compilation, timing analysis, place-and-route, bitstream generation and device programming for Intel FPGA product families, integrating workflows used in digital design teams from semiconductor research projects to aerospace programs. Quartus Prime is used by engineers engaged with device vendors, standards bodies, academic laboratories and industry consortia.
Quartus Prime aggregates capabilities for RTL designers who work with languages and standards such as Verilog, VHDL, SystemVerilog, and toolchains influenced by Synopsys and Cadence Design Systems. The suite incorporates synthesis engines, static timing analysis comparable to tools from Mentor Graphics (now Siemens EDA), place-and-route functionality analogous to flows seen in Xilinx (now part of AMD), and device programming interfaces that interact with hardware from Intel Corporation and partner vendors. Typical users include teams from NASA, European Space Agency, Airbus, and academic groups at institutions like MIT, Stanford University, and University of Cambridge.
Quartus Prime evolved from earlier FPGA tools developed by companies such as Altera Corporation prior to its acquisition by Intel Corporation in 2015. Its lineage traces through product families and releases shaped by market forces including competitive responses to Xilinx tools, cooperative work with standards bodies such as IEEE for HDL specifications, and adoption by consortia like OpenPOWER and research programs funded by DARPA. Development milestones include integration of high-level synthesis accommodations responding to innovations promoted at conferences like Design Automation Conference and collaborations with EDA partners including Synopsys, Cadence Design Systems, and Siemens EDA.
Quartus Prime combines synthesis, fitting, timing analysis and programming with features such as hierarchical design support, incremental compilation, design partitioning, floorplanning and power estimation. Architecturally it exposes interfaces to synthesis tools influenced by Synopsys Synplify and timing models aligned with IEEE 1800-2017 standards. It supports integration with system-level tools embraced by companies such as Arm Limited and NVIDIA for embedded processing subsystems, and includes instrumentation compatible with debugging tools like those from Tektronix and Keysight Technologies. Quartus Prime also provides IP catalog management and parameterizable IP blocks used in projects by Intel Corporation partners and customers.
Quartus Prime is offered in multiple editions reflecting commercial and academic markets: Standard/Pro/Prime variants tailored to different device families and licensing models often comparable to tiers used by Cadence Design Systems and Synopsys. Licensing options include node-locked and floating licenses managed via systems akin to FlexNet and enterprise agreements used by organizations such as Lockheed Martin and Boeing. Academic programs and university labs may obtain campus licenses through arrangements similar to those arranged by National Science Foundation-funded research centers.
Quartus Prime targets Intel FPGA families including devices from the Stratix, Arria and Cyclone lines originally marketed by Altera Corporation and later rebranded by Intel Corporation. It provides backend flows for device architectures used in products by companies like Cisco Systems, Huawei, Samsung Electronics, and Apple Inc. in specialized subsystems. Compatibility matrices reflect relationships with board vendors such as Terasic Technologies and module suppliers participating in RISC-V ecosystems, and interoperability testing with operating systems including Microsoft Windows and Red Hat Enterprise Linux.
Quartus Prime sits at the center of FPGA design flows that include front-end HDL development using editors and version control systems such as GitHub, GitLab, and Perforce. It integrates with simulation and verification frameworks from ModelSim by Siemens EDA and co-simulation setups referencing testbenches used in projects at Lawrence Livermore National Laboratory and CERN. Workflows often connect to PCB toolchains from Cadence Design Systems and Mentor Graphics for system integration, and to continuous integration systems such as Jenkins or GitLab CI in enterprise settings.
Performance characteristics of Quartus Prime are evaluated in industry benchmarks and comparisons with competitors like Xilinx Vivado; metrics include compile time, logic utilization, jitter, and static timing closure. Limitations historically cited by practitioners involve scalability on very large designs, memory and CPU requirements similar to those documented in reports from IEEE Design & Test and constraints in incremental compile granularity that design teams at Intel Corporation and partners have addressed in successive releases. Users performing high-frequency designs reference timing closure guidance originating from publications presented at International Symposium on Field-Programmable Gate Arrays.
Quartus Prime supports extensibility through Tcl-based scripting and APIs that enable automation used by engineering groups at Boeing, Northrop Grumman, and research labs like MIT Lincoln Laboratory. Third-party IP vendors such as Synopsys, ARM Limited, and niche suppliers in the FPGA marketplace provide IP cores and verification suites compatible with Quartus flows. The ecosystem includes board support packages from Terasic Technologies, debugging plugins from Texas Instruments and connectors into higher-level frameworks promoted by RISC-V International.
Category:Electronic design automation