Intel Core (microarchitecture)
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| Intel Core (microarchitecture) | |
|---|---|
| Name | Intel Core (microarchitecture) |
| Designer | Intel Corporation |
| Produced | 2006–2010 |
| Architecture | x86-64 (Intel 64) |
| Microarchitecture | Core |
| Process | 65 nm, 45 nm |
| Cores | 1–4 |
| Predecessor | Pentium M, NetBurst |
| Successor | Nehalem |
Intel Core (microarchitecture) The Intel Core microarchitecture is a family of microprocessor designs developed by Intel Corporation and introduced in 2006 as a follow-up to the Pentium M and a replacement for the NetBurst microarchitecture. It formed the foundation for mainstream Intel Core 2 processors and influenced later Nehalem (microarchitecture) and Sandy Bridge designs. The microarchitecture emphasized improved energy efficiency, increased instructions per cycle, and refined branch prediction relative to prior Intel products.
Overview and development
Development of the Core microarchitecture occurred at Intel engineering sites including Intel Israel Development Center, with program management involving executives such as Paul Otellini and architects who previously worked on Pentium M and P6 microarchitecture. The project was motivated by competitive pressure from Advanced Micro Devices products like Athlon 64 and broader industry moves exemplified by ARM Holdings and the Mobile computing market exemplars such as Apple Inc. portable systems. The roadmap milestones included shifts from 65 nm to 45 nm process nodes at fabrication plants such as Intel Fab 11X and Intel Fab D1D. Manufacturing yields and thermal targets were coordinated alongside partners including Taiwan Semiconductor Manufacturing Company discussions, while marketing and platform initiatives involved OEMs like Dell, HP Inc., Lenovo, Acer Inc., and Asus.
Design decisions were influenced by earlier successes in the Pentium M family which itself descended from the P6 microarchitecture lineage used in processors like Pentium III. The microarchitecture aimed to address drawbacks of the Pentium 4 era realized in the NetBurst line, notably the long pipeline and high power dissipation seen in Prescott. Intel announced the new product family at events including Intel Developer Forum sessions, and competitive demonstrations were staged at trade shows such as COMPUTEX and CES.
Architecture and microarchitecture features
Core integrated features common to the family include an x86-64 compatible instruction set architecture (Intel 64), support for SSE3 and later SSE4 extensions, and enhancements to the memory subsystem and bus interfaces used by platforms such as Intel 965 Express Chipset and Intel 4 Series Chipset. Microarchitectural innovations drew from research areas like speculative execution, out-of-order execution, and micro-op fusion, and implemented improved branch predictors building on techniques used in Itanium research and earlier P6 derivatives.
The design included widened instruction decode and retirement stages compared with Pentium M, and added unified integer and floating-point execution scheduling similar to elements found in IBM POWER and Sun Microsystems designs. Integration with system-level technologies such as Intel Virtualization Technology and Intel Trusted Execution Technology was implemented for enterprise and embedded markets, with ecosystem support from software vendors including Microsoft and Red Hat.
Pipeline, execution units, and cache hierarchy
The Core microarchitecture shortened overall pipeline depth compared to NetBurst, while increasing per-clock efficiency through wider decode and multiple execution ports. The pipeline combined elements of P6-style stages with modern superscalar features used in contemporary processors like AMD K8. Execution resources included multiple integer ALUs, SIMD units compatible with Intel MMX and Streaming SIMD Extensions, and micro-op caches and schedulers influenced by research from University of California, Berkeley and MIT collaborators.
Cache hierarchy used a multi-level scheme: relatively large L1 instruction and data caches, a unified L2 cache per core with inclusive or non-inclusive policies depending on stepping, and external support for L3 caches introduced later in successor families such as Nehalem. Cache coherency employed protocols compatible with multi-socket server designs similar to those used in Intel Xeon platforms and required chipset coordination with technologies like QuickPath Interconnect in subsequent generations. Memory controllers remained on-chipset for Core, linking to DDR2 SDRAM and later DDR3 SDRAM memory technologies.
Power management and thermal design
Power optimizations leveraged lessons from the Pentium M power-optimized design and included dynamic voltage and frequency scaling features marketed as Enhanced Intel SpeedStep Technology. Thermal design targeted lower thermal design power for laptop OEMs such as Apple Computer and Lenovo, enabling thinner and quieter systems showcased at events like Macworld. Techniques included clock gating, power gating of idle units, and optimized microcode to reduce pipeline stalls. Coordination with platform firmware teams at companies like Insyde Software and American Megatrends ensured ACPI-compatible power states for enterprise clients including IBM and Sun Microsystems.
Thermal solutions from partners such as Delta Electronics and Foxconn were used in reference designs to meet operational limits and regulatory standards including those promulgated by EPA and energy labeling seen in regions like the European Union.
Performance, benchmarks, and variants
The Core microarchitecture delivered significant performance-per-watt improvements over NetBurst in benchmarks run by reviewers at publications like AnandTech, Tom's Hardware Guide, PC Magazine, and PCWorld. Popular benchmarking suites used included SPECint, SPECfp, SiSoftware Sandra, and real-world tests such as gaming titles from Valve Corporation and content creation workloads from Adobe Systems applications. Variants of the Core family included mobile-focused parts used in MacBook Pro models and desktop-oriented Intel Core 2 Duo and Core 2 Quad SKUs, with server versions in the Intel Xeon 3000 line.
Competitive comparisons often referenced contemporaries such as AMD Athlon 64 X2, AMD Phenom, and system-on-chip trends from Qualcomm. Subsequent microarchitectures like Nehalem and Sandy Bridge built upon Core’s foundations, integrating features such as on-die memory controllers and ring interconnects seen in later Intel product briefs. Industry recognition included performance leadership in mobile and mainstream client segments and influenced roadmaps discussed at events like Intel Developer Forum and Hot Chips.