Gate-all-around transistors

Gate-all-around transistors
Name	Gate-all-around transistor
Caption	Cross-sectional schematic of a multi-bridge-channel device
Type	Field-effect transistor
Developed by	TSMC, Samsung Electronics, Intel Corporation, GlobalFoundries
Introduced	2010s
Process node	5 nm, 3 nm
Successor	FinFET

Gate-all-around transistors are a class of field-effect transistor architectures in which the gate electrode surrounds the channel on all sides to provide superior electrostatic control. First deployed in production nodes during the 2020s, these devices extend work on multi-gate concepts developed by research groups at institutions like IMEC, Georgia Institute of Technology, and CEA-Leti. They are central to roadmaps published by Semiconductor Industry Association, International Roadmap for Devices and Systems, and foundry partners such as TSMC and Samsung Electronics.

Introduction

Gate-all-around designs evolved from earlier multigate devices such as FinFET and planar double-gate transistors pursued at Stanford University and Massachusetts Institute of Technology. Key industry players including Intel Corporation, GlobalFoundries, ARM Holdings, and NXP Semiconductors integrated the concept into node strategies alongside scaling metrics used by United Microelectronics Corporation and Sony Corporation. Academic milestones from groups at University of California, Berkeley, University of Cambridge, and Peking University influenced process choices now appearing in fabrication lines owned by Micron Technology and SK Hynix.

Structure and Operation

Gate-all-around devices enclose a semiconducting channel—implemented as a nanowire, nanosheet, or multi-bridge channel—by a gate stack that can include high-k dielectrics and metal gates developed in collaboration with materials teams at DuPont, BASF, and Applied Materials. The electrostatic control improves short-channel behavior characterized in device models referenced by Cadence Design Systems and Synopsys. Charge transport and subthreshold swing behavior draw on theoretical frameworks from researchers associated with NVIDIA Research, IBM Research, and Bell Labs. Experimental characterization often uses metrology platforms from KLA Corporation and ASML Holding.

Fabrication and Materials

Manufacturing routes originate from techniques like sacrificial-layer release and selective etch first demonstrated in labs at IMEC and CEA-Leti and later industrialized by TSMC, Samsung Electronics, and Intel Corporation. Channel materials include silicon, silicon-germanium, and III-V alternatives explored at Purdue University and Tsinghua University, with epitaxy tools supplied by Tokyo Electron Limited and Lam Research Corporation. Gate dielectrics leverage high-k films such as hafnium oxide researched at Oak Ridge National Laboratory and Lawrence Berkeley National Laboratory, while metal gate stacks draw on alloys developed at BASF and Dow Chemical Company.

Performance and Advantages

Gate-all-around architectures deliver improved electrostatic integrity, reduced leakage, and enhanced drive current compared with FinFET in equivalent footprints, claims validated in benchmarks from Intel Corporation, TSMC, and Samsung Electronics. They enable tighter threshold control affecting products from Apple Inc., Qualcomm, Broadcom Inc., and MediaTek by improving subthreshold swing and scaling efficiency metrics used by ARM Holdings partners. Power-performance-area improvements have been documented in collaborations with Electronic Design Automation vendors like Cadence Design Systems and Synopsys and in publications coauthored with researchers at ETH Zurich and University of Illinois at Urbana–Champaign.

Challenges and Limitations

Adoption requires overcoming challenges in patterning and variability addressed by lithography systems from ASML Holding and by self-aligned processes developed at IMEC and Intel Corporation. Yield and thermal budget issues intersect with backend processes used by GlobalFoundries and TSMC; reliability concerns such as bias temperature instability and hot carrier injection are studied at NIST and SEMATECH. Cost pressures and capital expenditures influence roadmap decisions discussed by International Sematech, Semiconductor Industry Association, and foundry alliances including UMC and SMIC.

Applications and Industry Adoption

Gate-all-around transistors are used in logic and low-power applications for system-on-chip customers such as Apple Inc., Samsung Electronics, Qualcomm, and NVIDIA Corporation. They underpin advanced nodes in consumer products from Sony Corporation and data-center processors from Intel Corporation and AMD. Adoption timelines are influenced by partnerships between foundries like TSMC and research consortia including IMEC and EUROPRACTICE, with supply chains involving equipment vendors ASML Holding, Tokyo Electron Limited, and Lam Research Corporation.

Future Developments and Research Directions

Ongoing work focuses on heterogeneous channel materials (III-V, 2D semiconductors) pursued at MIT, Stanford University, and Peking University and on integration strategies led by IMEC and CEA-Leti. Co-design of devices and circuits with EDA vendors Cadence Design Systems and Synopsys and system architects at ARM Holdings and NVIDIA Corporation will shape next-generation nodes. Policy and funding from agencies such as DARPA, European Commission, and National Science Foundation support projects targeting beyond-CMOS paradigms, including spintronics and quantum device hybrids studied at IBM Research and Microsoft Research.

Category:Transistor types