Synchronous dynamic random-access memory

Synchronous dynamic random-access memory is a type of DRAM where the operation of the external interface is synchronized by an external clock signal. This fundamental architectural shift, pioneered by companies like Samsung and Micron Technology, allowed memory to operate in lockstep with the CPU's system bus, dramatically improving performance over earlier asynchronous designs. Its development in the early 1990s and subsequent dominance in the PC market throughout the late 1990s marked a critical evolution in computer memory technology, paving the way for modern high-speed memory standards.

Overview

The primary innovation of SDRAM was its synchronous interface, which coordinated all signal timing with the rising edge of the system clock from the memory controller. This allowed for more efficient pipelining of commands and enabled the memory chip to operate on a clock cycle basis rather than being tied to specific access time delays. The technology was standardized under the auspices of the Joint Electron Device Engineering Council, which published formal specifications to ensure compatibility across the industry. This standardization was crucial for its adoption in platforms ranging from Intel's Pentium-based systems to Sega's Dreamcast and Microsoft's original Xbox.

Technical specifications

SDRAM modules are characterized by their clock speed, which is expressed in megahertz, and their corresponding data transfer rate. Common speeds include PC-66, PC-100, and PC-133, denoting bus speeds of 66 MHz, 100 MHz, and 133 MHz respectively. The modules typically use a 3.3-volt power supply and feature a 168-pin dual in-line memory module form factor with two notches to prevent incorrect installation. Key timing parameters, such as CAS latency, are critical for performance and are defined in the JEDEC standards. The internal architecture is divided into multiple banks, allowing one bank to precharge while another is being accessed, which hides latency and improves overall throughput.

Architecture and operation

Internally, an SDRAM chip is organized into several independent memory banks, typically two or four, that can operate simultaneously. A fundamental command set, including Activate, Read, Write, and Precharge, is issued by the memory controller on each clock cycle. This command-based protocol allows for complex operations like burst transfers, where a single read or write command is followed by a sequence of data words on consecutive clock cycles without further commands. The interface also incorporates a mode register, programmed upon initialization, which configures parameters like burst length and CAS latency. This architecture significantly reduced wait states compared to the FPM and EDO DRAM that preceded it.

Variants and generations

While the original single data rate SDRAM was the mainstream standard, several specialized variants emerged. GDDR SDRAM, developed for graphics applications by companies like NVIDIA and ATI Technologies, evolved separately with higher bandwidths for use in GPUs. The primary evolutionary path for main memory was the transition to DDR SDRAM, which transfers data on both the rising and falling edges of the clock signal, effectively doubling the data rate. Later generations, including DDR2 SDRAM and DDR3 SDRAM, continued this progression. Other niche variants included Mobile DDR for low-power devices and RDRAM, a competing synchronous architecture championed by Intel for the Pentium 4.

Applications and market history

SDRAM became the ubiquitous main memory for personal computers following its introduction with Intel's 430VX and 440BX chipsets and the rise of the Windows 95 and Windows 98 operating systems. Its performance was essential for the increasing demands of business software, early 3D gaming on platforms like the 3dfx Voodoo, and multimedia applications. Beyond the PC clone market, it was used in workstations from Sun Microsystems, networking equipment from Cisco Systems, and various embedded systems. Its production peaked around the year 2000 before being rapidly supplanted by DDR SDRAM, a transition accelerated by the launch of AMD's Athlon processor and Intel's Pentium 4 Willamette platform. Category:Computer memory Category:DRAM Category:Computer hardware standards