Generated by DeepSeek V3.2| PC-133 | |
|---|---|
| Name | PC-133 |
| Type | Synchronous dynamic random-access memory |
| Generation | SDR SDRAM |
| Related | PC-100, DDR SDRAM |
| Replaced by | DDR SDRAM |
PC-133. It is a standard for synchronous dynamic random-access memory modules, operating at a clock frequency of 133 MHz. This specification was a direct evolution of the earlier PC-100 standard, developed to meet the demands of faster central processing units and front-side bus speeds prevalent at the turn of the millennium. Its introduction provided a crucial performance boost for Intel's Pentium III and early Pentium 4 platforms, as well as Advanced Micro Devices' Athlon processors, before being superseded by double data rate technologies.
The defining characteristic of this memory standard is its 133 MHz clock signal, which provides a peak bandwidth of approximately 1.06 GB/s for a 64-bit wide module. It adheres strictly to the electrical and timing parameters defined for 133 MHz SDR SDRAM operation, requiring higher-grade dynamic random-access memory chips than its predecessor. Key parameters include a precise CAS latency of 3 and stringent requirements for signal integrity, governed by specifications from JEDEC. Module construction typically involved 168-pin DIMMs, with registered variants available for server applications to improve stability in systems with high memory loads.
The development was driven by the need for higher memory bandwidth to keep pace with escalating front-side bus speeds in mainstream personal computers. Following the success of PC-100, which was closely associated with the Intel 440BX chipset, major dynamic random-access memory manufacturers like Samsung Electronics, Micron Technology, and Hyundai Electronics collaborated on the faster specification. It was formally standardized around 1999, coinciding with the launch of Intel's Pentium III Coppermine processors and chipsets such as the Intel 815. The standard served as a final performance peak for single data rate architecture before the industry's decisive shift toward DDR SDRAM, which was being developed concurrently by companies like VIA Technologies and Advanced Micro Devices.
Modules were designed to be backward compatible with motherboards and chipsets designed for PC-100, though they would operate at the lower 100 MHz speed unless the BIOS and chipset explicitly supported the faster timing. Primary usage was in systems based on the Intel 815, VIA Apollo Pro133, and SiS 630 chipsets, which natively supported the 133 MHz front-side bus. It was also widely used with AMD's Athlon processors paired with chipsets like the VIA KT133. A critical limitation was that many older Intel 440BX-based systems could not officially support the standard due to chipset constraints, leading to unofficial overclocking by enthusiasts.
The standard enjoyed significant market success as a cost-effective performance upgrade during a transitional period in the late 1990s and early 2000s. It effectively extended the lifespan of the SDR SDRAM ecosystem while DDR SDRAM platforms matured. Variants included not only the standard 133 MHz modules but also higher-latency, lower-cost versions sold for the budget segment. The emergence of virtual channel memory by NEC and enhanced architectures from Rambus created competitive pressure, but the widespread industry support for the established DIMM form factor ensured its dominance in the mainstream market until DDR SDRAM prices became competitive.
Compared to its direct predecessor PC-100, it offered a 33% increase in clock speed and bandwidth. However, it was fundamentally outpaced by the emerging DDR SDRAM (e.g., DDR-266), which could transfer data on both the rising and falling edges of the clock signal, effectively doubling the data rate. It also stood in stark contrast to the competing but expensive Rambus DRAM (RDRAM) used in the Pentium 4's Intel 850 chipset, which offered higher bandwidth but at a significant cost premium and with greater complexity. Against later standards like DDR2 SDRAM, the architectural limitations of single data rate technology made it obsolete for all but the most legacy-conscious applications.