MIPS architecture

MIPS architecture
Name	MIPS architecture
Designer	John L. Hennessy
Bits	32-bit, 64-bit
Introduced	1985
Design	RISC
Endianness	Bi-endian
Page size	4 KB, 16 KB, 64 KB
Extensions	MIPS16, MIPS-3D, MDMX
Open	Yes (MIPS Open)
Predecessor	Stanford MIPS
Successor	RISC-V, LoongArch

Contents

History and development
Architecture design
Instruction set
Implementations
Applications and market impact
See also

MIPS architecture. The MIPS architecture is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Computer Systems, founded by John L. Hennessy. Originating from academic research at Stanford University, it became one of the most influential RISC designs, powering systems from Silicon Graphics workstations to early PlayStation and Nintendo 64 video game consoles. Its clean, efficient design principles emphasizing hardware simplicity and compiler optimization have left a lasting legacy on microprocessor development.

History and development

The architecture's foundations were laid in the early 1980s through the Stanford MIPS research project led by John L. Hennessy. This academic work evolved into a commercial venture with the founding of MIPS Computer Systems in 1984, which released its first commercial implementation, the R2000, in 1985. The company and its architecture were later acquired by Silicon Graphics (SGI), which utilized the processors extensively in its Indigo and Onyx workstation and server lines. After various corporate transitions, including ownership by Broadcom and Imagination Technologies, the architecture was made open standard through the MIPS Open initiative, though its influence has since been challenged by the rise of ARM architecture and the open-source RISC-V.

Architecture design

The design is a classic load/store architecture, a hallmark of the RISC philosophy, where operations are performed only on processor registers, and separate instructions handle memory access. It features a fixed 32-bit instruction length for simplicity in decoding and a relatively small set of uniform instructions. The architecture employs a pipeline (computing) design, famously requiring compilers to handle branch delay slots to maintain efficiency. Key architectural components include a dedicated program counter, 32 general-purpose registers, and special registers like the HI and LO registers for multiplication and division results. Support for both big-endian and little-endian byte ordering (bi-endianness) was added in later revisions.

Instruction set

The core instruction set is categorized into several types: arithmetic (e.g., ADD, SUB), logical (e.g., AND, OR), data transfer (e.g., LW for load word, SW for store word), and control flow (e.g., BEQ for branch on equal, J for jump). A defining feature is its use of three-operand formats (e.g., `ADD $d, $s, $t`), which provides flexibility for compilers. Over time, the ISA was extended with specialized instruction sets like MIPS16 for improved code density in embedded systems, MIPS-3D for graphics acceleration, and MDMX for multimedia applications. The architecture also defines precise exceptions and a software-managed translation lookaside buffer (TLB) for memory management.

Implementations

Early landmark implementations include the R2000 and its floating-point co-processor, the R2010, followed by the R3000 which gained widespread use in systems like the PlayStation. The introduction of the 64-bit R4000 by MIPS Technologies marked a significant evolution, featuring superscalar execution. Later generations, such as the R5000, R10000, and the MIPS32/MIPS64 architecture families from MIPS Technologies, were used in products from companies like Cisco Systems routers, Texas Instruments digital signal processors, and NEC electronics. Modern implementations are often licensable cores from Imagination Technologies or designs from the Chinese Academy of Sciences like the Godson processor, which evolved into the Loongson series.

Applications and market impact

Historically, it achieved major success in the 1990s within high-performance computing, notably powering the Silicon Graphics Indigo and Challenge series, and in the consumer electronics space as the CPU for the original PlayStation, PlayStation 2, and Nintendo 64. Its design efficiency made it a dominant force in the embedded systems market, found in networking equipment from Juniper Networks and Linksys, printers from HP, and automotive systems. While its market share in high-performance computing and consumer devices waned with the ascendancy of the ARM architecture and x86, its architectural concepts profoundly influenced later ISAs, including DEC Alpha, HP PA-RISC, and the contemporary RISC-V project.