RISC-V

RISC-V
Name	RISC-V
Designer	University of California, Berkeley
Bits	32, 64, 128
Version	20191213
Encoding	Variable
Endianness	Little
Page size	4 KiB
Extensions	I, M, A, F, D, C, ...
Website	https://riscv.org

RISC-V. RISC-V is an open standard instruction set architecture based on established reduced instruction set computer principles. The architecture was originated in 2010 by researchers in the Parallel Computing Laboratory at the University of California, Berkeley, led by professors David Patterson and Krste Asanović. Governed by the non-profit RISC-V International, the standard is freely available for any use, fostering a global ecosystem of hardware and software innovation across computing domains from embedded systems to high-performance supercomputers.

Overview

As a modern, open ISA, it provides a foundation for processor design unencumbered by licensing fees or proprietary restrictions. The base integer instruction sets are simple and stable, while a modular system of standard extensions allows designers to tailor a processor for specific performance, power, and area targets. This open model has attracted participation from major technology firms, academic institutions, and startups, enabling collaborative development and reducing fragmentation. The governance by RISC-V International ensures the architecture evolves through a ratified, consensus-driven process.

History and development

The project began in 2010 within the Parallel Computing Laboratory at University of California, Berkeley, a response to the complexity and licensing constraints of existing commercial ISAs like x86 and ARM. Key architects included Krste Asanović, David Patterson, and Andrew Waterman. The first workshop was held at Google in 2015, marking the start of broad industry engagement. To steward its development, the non-profit RISC-V Foundation was formed, later renamed RISC-V International and moving its headquarters to Switzerland. Major milestones include the ratification of the base specifications and critical extensions, with ongoing work managed through collaborative task groups.

Technical features

The architecture features a load-store design, 32 general-purpose integer registers, and a modular approach where the base ISA is extended with optional, standardized components. It supports multiple address spaces, including 32-bit, 64-bit, and 128-bit variants. The instruction format is highly regular and compressed using the standard C extension, improving code density. Other foundational features include support for both little-endian and big-endian memory access, a flat address space, and a privileged architecture specification defining machine, supervisor, and user modes for secure system operation.

Standard extensions

The modularity is realized through numerous ratified standard extensions, denoted by single letters. The I extension forms the base integer instructions, while M adds integer multiplication and division. The A extension provides atomic operations for synchronization in multi-core systems. For floating-point computation, the F and D extensions add single-precision and double-precision support, respectively. The C extension offers 16-bit compressed instructions to reduce program size. Other important extensions include V for vector processing, B for bit manipulation, and J for dynamically translated languages, allowing for highly specialized processor implementations.

Implementations and applications

Implementations span from open-source cores like those from SiFive, the lowRISC project, and the Berkeley Out-of-Order Machine, to commercial products from companies such as NVIDIA, Western Digital, and Alibaba Group. Applications are vast, including microcontrollers in Internet of Things devices, embedded controllers in Western Digital hard drives, application processors in Samsung Electronics smartphones, and accelerators within NVIDIA GPUs and Google Tensor Processing Units. High-performance computing efforts are also underway, with projects in the European Processor Initiative and plans for Frontier (supercomputer)-class machines.

Ecosystem and community

The ecosystem is supported by RISC-V International, which hosts working groups, ratifies specifications, and organizes events like the RISC-V Summit. Major corporate members include Google, Intel, Qualcomm, and NVIDIA. Software support is extensive, with mainline ports of the Linux kernel, the GNU Compiler Collection, and the LLVM toolchain. Academic involvement remains strong through institutions like University of California, Berkeley and the ETH Zurich. The open nature fosters collaboration across borders, with significant contributions from organizations in the United States, Europe, and China, driving rapid innovation in the processor industry.

Category:Instruction set architectures Category:Open hardware Category:Computer standards