MESI protocol

MESI protocol
Name	MESI protocol
Inventor	Intel
Based on	Write-once protocol
Used in	Pentium Pro, x86, PowerPC

MESI protocol. The MESI protocol is a widely used cache coherency protocol employed in multiprocessor systems to maintain data consistency between caches. It defines four distinct states—Modified, Exclusive, Shared, and Invalid—that a cache line can occupy, governing how multiple cores interact with shared main memory. The protocol's operations are coordinated through a snooping mechanism that monitors a shared system bus, ensuring all caches observe a coherent view of memory. Its development was instrumental for the performance of symmetric multiprocessing systems from companies like Intel and IBM.

Overview

The protocol was developed to solve the cache coherence problem inherent in systems with multiple processors, such as those based on the x86 architecture. It is a snoopy protocol that relies on a shared front-side bus for communication between CPUs and memory controllers. The design builds upon earlier concepts like the Write-once protocol and was notably implemented in Intel's Pentium Pro processor. Its adoption enabled more efficient parallel computing by reducing unnecessary traffic to DRAM.

Protocol states

Each cache line is tagged with one of four states defined by the protocol. The **Modified** state indicates the line is dirty and exists only in the current cache, requiring a write-back to main memory when evicted. The **Exclusive** state signifies the line is clean but solely held by this cache. The **Shared** state denotes the line is clean and potentially held in other caches, such as those in a dual-core processor. The **Invalid** state marks the line as not present or stale, often triggered by a write operation from another processor core observed via bus snooping.

State transitions

Transitions are triggered by local CPU requests or bus transactions observed via snooping. A read miss may cause a transition to **Shared** or **Exclusive**, depending on a bus signal like a shared-response from another cache controller. A write by the local CPU typically requires an invalidating broadcast to other caches, moving the line to **Modified**. Observing a read-for-ownership on the bus from another Intel core forces a transition to **Invalid** or prompts a write-back if in the **Modified** state. These rules prevent race conditions in systems like the PowerPC architecture.

Bus operations

The shared system bus carries specific operations that drive state changes. A **Read** operation is issued on a cache miss, potentially receiving a shared signal from a snooping cache. A **Read-for-Invalid** or **Read-for-Ownership** is used to obtain exclusive ownership before a write. An **Invalidate** command broadcasts the intent to modify data, forcing other caches to discard their copies. A **Write-back** operation occurs when a **Modified** line is evicted, updating main memory. These operations are fundamental to snoopy coherence implementations in architectures like x86-64.

Performance and optimizations

While effective, the basic protocol can generate substantial bus traffic, leading to optimizations. The **Owned** state, introduced in the MOESI protocol, allows a dirty line to be shared, reducing write-backs. **Dirty sharing** techniques, as seen in some AMD processors, minimize accesses to SDRAM. **Silent evictions** of **Exclusive** lines avoid unnecessary bus signals. Directory-based coherence, used in larger systems like NUMA machines from Silicon Graphics, replaces snooping to scale beyond bus limitations. Such enhancements address bottlenecks in high-performance computing clusters.

Related protocols

Several protocols evolved from or alongside this one. The **MOESI protocol**, developed by AMD for its Athlon 64 and used in the HyperTransport-based Opteron, adds an Owned state. The **MESIF protocol**, introduced by Intel for the QuickPath Interconnect in the Nehalem microarchitecture, includes a Forward state to designate a preferred responder. The **Dragon protocol**, from Xerox PARC, is an update-based alternative. The **MSI protocol** is a simpler three-state precursor. These variants are employed in different multiprocessor systems, such as those using the ARM architecture or IBM's POWER architecture.

Category:Cache coherency protocols Category:Computer memory Category:Parallel computing