Intel QuickPath Interconnect

Intel QuickPath Interconnect. It is a point-to-point processor interconnect architecture introduced by Intel in 2008, marking a fundamental shift from the traditional front-side bus used in earlier systems. The technology was designed to provide high-bandwidth, low-latency communication between the central processing unit, memory controllers, and other system components. Its development was a direct competitive response to the HyperTransport technology championed by Advanced Micro Devices.

Overview

The introduction of this interconnect coincided with the launch of the Nehalem microarchitecture, representing a core component of the Intel Xeon and high-end Intel Core processor families. It fundamentally rearchitected how processors accessed memory and communicated with each other in multi-socket systems, moving the memory controller from the northbridge onto the processor die itself. This architectural change significantly reduced memory latency and increased bandwidth, addressing bottlenecks prevalent in front-side bus designs. The technology was pivotal for scalable performance in servers, workstations, and high-end desktop platforms.

Architecture and Design

The architecture employs a distributed shared memory design, utilizing multiple high-speed serial links in a point-to-point topology. Each physical link consists of a pair of twenty-bit wide, unidirectional lanes operating in a full-duplex manner, enabling simultaneous send and receive operations. The design integrates a routing table within each processor to manage data packet flow across the network, supporting complex system configurations including Non-Uniform Memory Access architectures. Key components include the integrated memory controller, the QuickPath Interconnect logic block, and a layered protocol stack handling physical, link, and routing layers. This separation ensures reliable packet delivery and efficient system coherency across multiple sockets.

Technical Specifications

The initial generation offered a data transfer rate of up to 6.4 gigatransfers per second per lane, with each unidirectional link providing a raw bandwidth of up to 12.8 GB/s in full-duplex mode. The physical layer utilized differential signaling with embedded clocking, similar to PCI Express, to ensure signal integrity at high speeds. Supported system topologies included straight point-to-point links, multi-drop configurations for glueless multi-processor setups, and the use of Intel 7500 series chipsets for I/O expansion. The protocol maintained cache coherency across the entire system using a directory-based MESIF protocol, an enhancement of the classic MOESI protocol.

Implementation and Usage

It was first implemented in processors based on the Nehalem and Westmere microarchitectures, such as the Intel Core i7-9xx series and the Intel Xeon 5500 series. Its primary deployment was in multi-socket servers and high-performance computing systems from original equipment manufacturers like Dell, Hewlett-Packard, and IBM. The technology was also a critical enabler for the Intel Xeon processor E7 family and certain iterations of the Intel Itanium processor family, codenamed Tukwila. Its use was largely confined to the enterprise and enthusiast segments, as mainstream desktop platforms typically utilized a direct Direct Media Interface link to the Platform Controller Hub.

Comparison with Other Interconnects

The primary competitor was Advanced Micro Devices' HyperTransport, which also employed a point-to-point, packet-based architecture. While both technologies aimed to eliminate the front-side bus bottleneck, a key architectural difference was the integration of the memory controller; this interconnect placed it on-die, whereas contemporary HyperTransport implementations often connected to an external controller. Compared to the older front-side bus used in systems like the Intel Core 2, it offered vastly superior scalability and bandwidth. Later industry standards like PCI Express and Compute Express Link serve different primary functions, focusing on I/O connectivity and accelerator attachment, respectively, rather than core CPU-to-CPU coherence.

Evolution and Successors

The technology evolved through several speed increments, reaching 9.6 GT/s in later implementations for the Ivy Bridge-EX and Haswell-EX generations. It was ultimately superseded by the Ultra Path Interconnect, introduced with the Skylake-SP microarchitecture. Ultra Path Interconnect doubled the per-lane data rate and introduced architectural improvements for enhanced scalability in dense multi-socket systems. This progression continued Intel's focus on high-bandwidth, coherent interconnects critical for data center workloads, influencing the development of newer fabrics like the Compute Express Link standard. Category:Intel microprocessors Category:Computer buses Category:Computer hardware standards