Infinity Fabric

Infinity Fabric. It is a high-speed, scalable SoC interconnect architecture developed by Advanced Micro Devices (AMD) to serve as the foundational communication fabric for its modern processors. First introduced with the Zen microarchitecture, it replaced the older HyperTransport link and is integral to the design of Ryzen, Epyc, and Radeon Instinct products. The fabric enables coherent data transfer between multiple cores, GPUs, memory controllers, and I/O units within a single die or across multiple chips in a package.

Overview

The architecture was unveiled as a cornerstone of AMD's return to high-performance computing, fundamentally enabling its Chiplet design strategy. It functions as a unified, coherent interconnect that binds together various intellectual property blocks, known as "Infinity Fabric IP blocks", across the entire SoC. This design philosophy allows for modular construction of processors, separating core complexes from I/O dies, which is exemplified in products like the Epyc server processors and Ryzen desktop CPUs. The fabric's operation is managed by the Scalable Data Fabric (SDF) and Scalable Control Fabric (SCF), ensuring low-latency communication and system coherence.

Architecture and Design

The technical design is bifurcated into two distinct layers: the data fabric and the control fabric. The data layer, often called the Scalable Data Fabric, handles the actual movement of data and memory traffic between cores, caches, and the memory controllers. The control layer, or Scalable Control Fabric, manages coherency, power states, and system configuration messages. It employs a packet-switched network-on-a-chip (NoC) topology, with its performance directly tied to the memory clock speed in earlier implementations, a relationship known as "Fabric Clock" or "FCLK". This architecture is central to the operation of the Zen, Zen 2, Zen 3, and Zen 4 cores.

Performance and Scalability

Its performance is a critical determinant of overall system throughput, particularly in multi-chip module designs like those used in Epyc and high-end Ryzen processors. Bandwidth and latency are optimized through physical SerDes links that can operate at speeds exceeding 20 Gbps, enabling coherent links between separate dies in a package, such as in the Epyc Genoa platform. Scalability is demonstrated in products like the AMD Instinct MI250X, which uses the fabric to interconnect multiple GPU dies and HBM stacks. The introduction of technologies like AMD 3D V-Cache also relies on this interconnect for attaching additional SRAM cache dies directly to the compute dies.

Implementations and Products

The technology debuted commercially in 2017 with the first-generation Ryzen processors based on the Zen core and the Naples server platform. It is a defining feature of all subsequent AMD architectures, including the chiplet-based Zen 2 processors found in the Ryzen 3000 series and Rome servers. In the data center, it enables the coherent connectivity in the AMD Instinct accelerator family, such as the MI250, and is fundamental to exascale supercomputers like Frontier. The fabric also underpins the PlayStation 5 and Xbox Series X/S SoCs, which are based on semi-custom Zen 2 designs.

Comparison with Alternatives

In the market, it is most directly contrasted with Intel's interconnect technologies, such as the Ultra Path Interconnect (UPI) used in Xeon processors and the proprietary mesh architecture within Core CPUs. Unlike Intel's monolithic mesh, AMD's fabric is designed explicitly for disaggregated, chiplet-based designs, offering manufacturing and scalability advantages. For coherent GPU connectivity, it competes with NVIDIA's NVLink technology, though NVLink is primarily focused on GPU-to-GPU communication in systems like the NVIDIA DGX, while AMD's solution is a holistic CPU-to-GPU and CPU-to-CPU fabric. Its open standard counterpart for cache-coherent interconnects is Compute Express Link (CXL), which AMD has begun to integrate for advanced memory expansion.

Category:Advanced Micro Devices Category:Computer buses Category:Microprocessors