EMIB

EMIB. Embedded Multi-Die Interconnect Bridge is an advanced semiconductor packaging technology developed by Intel. It enables high-density, high-bandwidth connections between heterogeneous dies—such as CPUs, GPUs, HBM, and specialized accelerators—within a single package by embedding small silicon bridge chips into the organic package substrate. This approach provides a cost-effective and flexible alternative to traditional 2.5D integration methods like silicon interposers, allowing for improved performance and power efficiency in complex SoC designs.

Overview

The EMIB technology functions by placing thin silicon bridge dies, fabricated with multiple layers of fine-pitch interconnect wiring, into cavities formed within a standard organic package substrate. These bridges are not a full layer beneath the dies like a silicon interposer; they only exist precisely where high-density connections are required between adjacent chiplets. This selective embedding allows for direct, short electrical pathways between dies using extremely dense microbump arrays, significantly increasing bandwidth and reducing latency and power consumption compared to routing signals through the substrate. Key implementations of EMIB can be found in products like Intel's Stratix 10 FPGAs, which integrate transceiver tiles and high bandwidth memory, and later client processors.

Technology and Architecture

An EMIB package's architecture consists of several core components: the primary organic laminate substrate, one or more embedded silicon bridge dies, and the disparate functional dies mounted on top. The bridge dies are typically manufactured using a modified back-end-of-line process on 300 mm wafers, creating interconnect layers with line/space geometries as fine as 2 µm or less, far exceeding the routing density of the organic substrate. Connections between the top dies and the bridge are made through arrays of solder microbumps, while the bridge itself is connected to the substrate's wiring through larger C4 bumps. This hybrid structure allows the package to utilize the cost-effective substrate for power delivery and most I/O, while the silicon bridge provides a short, high-performance data highway only where needed.

Applications and Use Cases

EMIB technology has been deployed to enable a variety of multi-chip architectures. A prominent early application was in Intel's Stratix 10 FPGAs, where it connected the core FPGA fabric to high-speed 56G SerDes transceiver chiplets and stacks of HBM2 memory. In the client computing space, it has been used in products like the Kaby Lake-G processor, which integrated an Intel CPU with a Radeon GPU from AMD and HBM2 memory on a single package. The technology is also foundational to Intel's broader chiplet-based design strategy, evident in advanced server products and planned for future integrations involving optical I/O chiplets and novel CXL-attached devices.

Comparison with Other Packaging Technologies

Compared to a monolithic SoC, EMIB offers the yield and cost benefits of disaggregating large dies into smaller chiplets while maintaining high interconnect performance. Against full-silicon 2.5D integration using a passive silicon interposer—pioneered by companies like Xilinx and TSMC with its CoWoS platform—EMIB is often more cost-effective as it uses less expensive silicon and avoids the thermal and mechanical challenges of a large, brittle interposer layer. However, for applications requiring extremely dense, full-area interconnection between many dies, interposer-based approaches may still offer advantages. EMIB also differs from fan-out wafer-level packaging technologies like those from ASE Group or TSMC's InFO, which are better suited for smaller form factors and lower I/O counts.

Development and Manufacturing

The development of EMIB involved significant research into materials science, thermomechanical modeling, and precision assembly processes. Key manufacturing challenges included achieving reliable embedding of the thin bridge dies into the substrate without causing warpage or delamination, and perfecting the microbump bonding process for high yield. Intel performs the bridge die fabrication and the final assembly and test at its own advanced packaging facilities, such as those in Chandler, Arizona. The technology leverages existing flip chip infrastructure but requires specialized equipment for precise bridge placement and the subsequent build-up of substrate layers around it.

History and Background

Research into embedded bridge concepts began at Intel in the early 2010s, driven by the need for more scalable and economical interconnect solutions beyond traditional PCB-level integration. The technology was first publicly disclosed around 2014 and entered commercial production with the Stratix 10 FPGA in 2017. Its development was part of a broader industry shift toward heterogeneous integration and chiplet architectures, a trend also being pursued by competitors like AMD with its Infinity Fabric and TSMC with its 3D Fabric portfolio. EMIB represents a key milestone in Intel's packaging roadmap, preceding and later being combined with its Foveros 3D stacking technology to create complex hybrid packages.