Yices

Yices
Name	Yices
Developer	SRI International
Released	2004
Latest release	2.x (various updates)
Operating system	Linux, macOS, Microsoft Windows
License	Proprietary (commercial) and free binaries for research

Yices is a satisfiability modulo theories (SMT) solver developed at SRI International for automated reasoning, formal verification, and symbolic analysis. It provides decision procedures and heuristics to determine the satisfiability of logical formulas over combinations of theories and is used in academic research, industrial verification, tools for software analysis, and hardware design flows. The tool has influenced and interoperated with a range of verification frameworks, model checkers, and theorem provers.

Overview

Yices originated at SRI International's Computer Science Laboratory and was publicly introduced in the mid-2000s, joining a family of SMT solvers including Z3 (theorem prover), CVC4, CVC5, Boolector, MathSAT, OpenSMT, veriT, and STP (solver). It targets satisfiability modulo theories problems arising from projects at institutions such as Stanford University, Massachusetts Institute of Technology, University of California, Berkeley, Princeton University, and industrial partners including Intel Corporation and ARM Holdings. Yices integrates into verification ecosystems alongside model checkers and static analyzers like CBMC, Frama-C, SPIN, NuSMV, Dafny, KLEE, SMTInterpol, and SeaHorn. It has been cited in work from conferences and venues such as CAV, CADE, ICFP, POPL, TACAS, SAT Conference, IJCAR, LICS, and FMCAD.

Features and Architecture

Yices implements a modular architecture combining a Boolean SAT core with theory solvers for arithmetic and data types, designed to support incremental solving, push/pop contexts, and model generation. Its architecture parallels designs in DPLL(T), conflict-driven clause learning, and architecture patterns seen in Z3 (theorem prover) and CVC4. It includes support for bit-vectors relevant to ARM Holdings and Intel Corporation processor verification, arrays leveraged by tools like KLEE and CBMC, and uninterpreted functions used in symbolic modeling at Stanford University. Yices exposes APIs for embedding in systems such as LLVM Project-based tools, GCC plugins, and proprietary flows at vendors like Samsung Electronics and Qualcomm. The solver's modularity allows composition with SMT-LIB standards and data formats adopted by SMT-LIB and tooling around GNU Project ecosystems.

Supported Theories and Solving Techniques

Yices supports a range of theories: linear integer arithmetic and linear real arithmetic used in research at MIT, nonlinear arithmetic interfaces similar to approaches in Mathematica and Maple, fixed-size bit-vectors employed in RISC-V and x86 architecture verification, arrays and extensional arrays relevant to ARM Holdings and Intel Corporation microarchitecture studies, algebraic datatypes adopted in Coq and Isabelle/HOL encodings, and uninterpreted functions common in Princeton University symbolic reasoning. Its solving techniques include DPLL(T) style SAT solving, theory propagation used in Z3 (theorem prover) comparisons, affine and simplex methods reminiscent of algorithms taught at California Institute of Technology, congruence closure methods similar to systems in ACL2, and model-based quantifier instantiation strategies used in CVC4 and SMTInterpol. Yices also offers tactics for quantifier handling inspired by approaches discussed at CAV and CADE.

Interfaces and Integration

Yices provides command-line interfaces, C and C++ APIs, and higher-level bindings inspired by integrations in projects such as Rosette and Dafny. It supports the SMT-LIB input language facilitating use with frontends like Sail (language) for processor modeling and with verification frameworks including Frama-C, SeaHorn, and KLEE. Yices has been wrapped for use in environments like Python (programming language), Haskell, and OCaml enabling research at University of Cambridge and ETH Zurich. Integrations with continuous integration and build systems traceable to Jenkins (software), Travis CI, and GitHub Actions are common in industrial verification pipelines at firms like Microsoft, Apple Inc., and Google LLC. Toolchains for hardware verification connecting to synthesis tools from Cadence Design Systems, Synopsys, and Mentor Graphics have also leveraged Yices.

Performance and Benchmarks

Yices has been evaluated on SMT-LIB benchmark suites and compared in empirical studies alongside Z3 (theorem prover), CVC4, Boolector, MathSAT, veriT, and STP (solver). Benchmarking results reported at venues such as SAT Conference, CAV, and TACAS illustrate Yices's competitive performance in linear arithmetic, bit-vector reasoning for ARM Holdings and Intel Corporation ISA models, and array-heavy verification tasks found in CBMC benchmarks. The solver's incremental features are often highlighted in regression suites used by IBM Research and academic groups at University of Oxford and University College London. Performance tuning has involved heuristics comparable to those developed in Z3 (theorem prover) and algorithmic strategies informed by work at ETH Zurich and Max Planck Institute for Software Systems.

Licensing and Development History

Yices development has been driven by researchers at SRI International with contributions and adopters across academia and industry. Licensing historically included free binaries for academic research and commercial licenses for enterprise use, similar to policies used by MathWorks and Synopsys for proprietary tools. Over time, Yices releases and versioning have been discussed in forums frequented by researchers from Carnegie Mellon University, University of Toronto, University of California, San Diego, and corporate users at Intel Corporation and ARM Holdings. Development roadmap items and community interactions have been coordinated with standards bodies around SMT-LIB and reported at conferences including CAV and TACAS.

Category:SMT solvers