SOI

SOI
Name	SOI
Type	Semiconductor substrate technology
Invented	1960s
Developer	Multiple research groups and companies
Application	Microelectronics, radio frequency, power devices

SOI

SOI is a semiconductor substrate technology used to fabricate integrated circuits, notable for incorporating a buried insulating layer to electrically isolate active regions. Initially developed alongside advances in silicon processing at institutions and firms, SOI has influenced roadmaps at companies and consortia and has been adopted across consumer electronics, aerospace, and telecommunications supply chains. The technology interrelates with fabrication nodes pursued by firms and standards set by international bodies and fabs.

Definition and abbreviations

In technical contexts, SOI commonly denotes a semiconductor approach with a buried oxide layer; related abbreviations encountered in industry literature include HSOI, FDSOI, PDSOI, and SIMOX. Historical and modern documents from Intel Corporation, IBM, GlobalFoundries, STMicroelectronics, and UMC use these acronyms alongside process names such as PD-SOI and FD-SOI. Trade organizations and research centers such as SEMI, IEEE, Imec, and CEA-Leti use standardized nomenclature for SOI variants when publishing roadmaps or presenting at venues like the International Electron Devices Meeting.

History and development

Early experiments with insulating layers beneath active silicon date to research at institutions like Bell Labs and University of California, Berkeley and to corporate groups within Fairchild Semiconductor and Motorola during the 1960s and 1970s. Commercialization milestones include production ramps by companies such as Soitec and trials by Intel Corporation for microprocessor prototypes in the 1990s. Research on ion implantation and wafer bonding at research centers like Stanford University, Massachusetts Institute of Technology, and CEA-Leti enabled processes such as SIMOX and Smart Cut, which were demonstrated in collaborations involving firms like IBM and STMicroelectronics. In the 2000s and 2010s, roadmap discussions at Semiconductor Research Corporation meetings and presentations at IEDM documented the maturation of fully depleted variants championed by European and Asian foundries, influencing product portfolios at GlobalFoundries and Samsung Electronics.

Technologies and variants

SOI technologies comprise several process families developed and promoted by different entities. The SIMOX approach, demonstrated by research partnerships including Rockwell International and later evaluated by Hitachi, uses high-dose oxygen implantation and annealing. The Smart Cut process, commercialized by Soitec through licensing agreements with foundries, relies on hydrogen-induced layer splitting and wafer bonding; licensees and collaborators have included STMicroelectronics and IBM. Variants emphasize device electrostatics and thermal behavior: PD-SOI (partially depleted), FD-SOI (fully depleted), and advanced flavors such as RF-SOI and SOI for power devices have been developed by firms such as NXP Semiconductors and Texas Instruments. Research architectures like silicon-on-nothing and silicon-on-sapphire were explored at universities including University of Cambridge and Tsinghua University for specialized applications. Foundry offerings from TSMC and UMC have incorporated SOI-derived modules into advanced nodes alongside bulk CMOS alternatives.

Applications and industry impact

SOI underpins microprocessors, radio-frequency front ends, and high-reliability space and defense electronics supplied by companies like Intel Corporation, Qualcomm, Qorvo, and Rohde & Schwarz. In mobile platforms, SOI-derived RF front-end modules have been deployed by chipset suppliers and handset makers such as Apple Inc. and Samsung Electronics, while automotive and industrial markets served by Infineon Technologies and NXP Semiconductors leverage SOI for improved isolation and latch-up immunity. Space agencies and contractors including NASA and Lockheed Martin have specified SOI-based parts for radiation tolerance. The technology has influenced supply chains through material suppliers like Soitec and through equipment vendors such as Applied Materials, ASML, and Lam Research that adapted tools for bonded wafers and thin-layer handling. Standards bodies and consortiums including SEMI and IEEE have tracked SOI in roadmap publications affecting capital investment decisions at fabs.

Advantages and limitations

Advantages cited by proponents at Intel Corporation and IBM include reduced parasitic capacitance, improved speed, and lower leakage in FD-SOI devices compared with bulk silicon nodes. RF-SOI variants offer isolation and substrate engineering benefits exploited by vendors like Skyworks Solutions and Qorvo for front-end modules. Radiation hardness and latch-up resistance have made SOI attractive to aerospace contractors and institutions such as ESA and NASA. Limitations include cost and supply constraints associated with specialized wafers produced by suppliers like Soitec, process integration complexity reported by foundries including GlobalFoundries, and thermal management challenges documented in studies from Imec and CEA-Leti. Design ecosystems and EDA flows from vendors such as Cadence Design Systems and Synopsys required extensions to model SOI-specific effects, influencing adoption curves among fabless firms like Qualcomm and Broadcom.

Related standards and terminology

Terminology and de facto standards for SOI processing and characterization have been discussed at venues run by SEMI, IEEE Electron Devices Society, and International Technology Roadmap for Semiconductors working groups; companies including Soitec and STMicroelectronics contributed white papers and technical notes. Measurement and qualification practices reference test methods developed in collaborations involving NIST and university labs such as UC Berkeley. Industry alliances and consortia, including SIA and regional clusters supported by agencies like BMBF and ANR, have published guidance on material specifications, wafer bonding protocols, and reliability metrics used by fabs including TSMC and GlobalFoundries.

Category:Semiconductor technology