Rocket Chip

Rocket Chip
Name	Rocket Chip
Developer	University of California, Berkeley Par Lab and SiFive
Released	2010s
Programming language	Chisel
Operating system	Linux
License	BSD license
Architecture	RISC-V

Rocket Chip is an open-source, parameterizable system-on-chip (SoC) generator for RISC-V processor cores and on-chip subsystems. Designed and maintained by researchers and engineers at University of California, Berkeley and commercialized by SiFive, Rocket Chip serves as a reference implementation for academic projects, commercial prototypes, and production designs integrating with toolchains from LLVM and GNU Project. The project emphasizes modularity, formal verification readiness, and integration with industry flows including FPGA prototyping and ASIC implementation.

Overview

Rocket Chip is built as a hardware generator that emits synthesizable Verilog using the Chisel hardware-construction language developed at Berkeley Architecture Research groups. It provides parameterizable cores, caches, interconnects, and peripherals suitable for integration with DRAM controllers, PCI Express, and Ethernet subsystems. The design is widely used in research at institutions such as MIT, Stanford University, ETH Zurich, and University of Cambridge, and by companies in the semiconductor industry for rapid prototyping. Tooling around Rocket Chip integrates with simulation frameworks like Verilator, formal tools from Cadence and Synopsys, and deployment flows targeting platforms from Xilinx and Intel FPGA.

Architecture

The core CPU in Rocket Chip is the Rocket core, a scalar, in-order RISC-V implementation that supports the RISC-V ISA base and standard extensions such as RV32I, RV64I, and optional C extension. The generator also supports alternate cores such as the out-of-order BOOM core from Berkeley Out-of-Order Machine research, and integrates vector units compatible with RISC-V V extension work from SiFive and academic partners. On-chip memory hierarchy components include parameterizable L1 instruction and data caches, L2 cache slices, and optional snooping coherence controllers for multiprocessor coherence protocols researched at Berkeley. The interconnect fabric is the TileLink protocol, a coherent on-chip network developed at UC Berkeley that facilitates communication between tiles, peripherals, and memory controllers. Peripheral IP blocks include UARTs, Platform-Level Interrupt Controller, CLINT, and debug modules compatible with RISC-V Debug Specification.

Implementation and Tooling

Rocket Chip’s reference implementation is written in Chisel and generates Verilog for downstream synthesis. The build and verification ecosystem uses sbt for Scala-based Chisel projects, FIRRTL for intermediate representation passes, and SymbiYosys or JasperGold for formal checks. Simulation workflows commonly use Verilator for cycle-accurate execution and integrate with software development kits such as OpenOCD and toolchains like GCC and LLVM/Clang for cross-compilation. For FPGA prototyping, Rocket Chip designs have been targeted to boards from Xilinx, Altera, and evaluation platforms supplied by SiFive. ASIC flows use synthesis and place-and-route tools from Cadence, Synopsys, and Mentor Graphics with physical libraries provided by foundries such as TSMC and GlobalFoundries.

Performance and Evaluation

Performance studies of Rocket Chip and derived cores have been published in venues including International Symposium on Computer Architecture and USENIX workshops, comparing core variants on benchmarks like SPEC CPU and PARSEC. The in-order Rocket core targets energy-efficient designs and demonstrates favorable area-performance tradeoffs relative to microarchitectures presented at International Symposium on Microarchitecture. Out-of-order BOOM cores implemented within the Rocket Chip ecosystem achieve higher single-thread IPC at increased area and power, as evaluated against designs cited in IEEE Micro and other conferences. Cache and coherence performance has been characterized using memory-intensive workloads from MiBench and industry suites, and integrated SoC prototypes have been measured for throughput on Ethernet and storage stacks using benchmarks curated by Storage Networking Industry Association partners.

Use Cases and Adoption

Rocket Chip is used as a research vehicle in universities such as UC Berkeley, Princeton University, and University of Illinois Urbana-Champaign, and by startups and established firms including SiFive, Western Digital, and academic spinoffs. Use cases include teaching computer-architecture courses at MIT and Berkeley, prototyping custom accelerators for machine learning integration with frameworks like TensorFlow and PyTorch via hardware-accelerator interfaces, and building domain-specific systems for edge computing and IoT devices. Commercial adoption includes tape-outs for specialized controllers in storage products from Western Digital and experimental SoC platforms from SiFive used by partners in the Internet of Things ecosystem.

History and Development

The Rocket Chip project originated at University of California, Berkeley within research groups focused on hardware-generation frameworks and the emerging RISC-V ecosystem. Key contributors include faculty and researchers associated with Berkeley Architecture Research teams who developed Chisel, TileLink, and the Rocket core as part of a broader push to create an open-source hardware stack. The technology has evolved through contributions from academic collaborators and industry partners such as SiFive and Western Digital, with major milestones reported alongside the growth of the RISC-V Foundation and subsequent standardization efforts. Continuous improvements have added support for multicore coherence, vector extensions, and commercial-grade tooling that enabled migration from academic prototypes to commercial silicon.

Category:RISC-V Category:Open-source hardware