LowRISC

LowRISC
Name	LowRISC
Type	Non-profit project
Founded	2013
Founder	University of Cambridge researchers
Location	Cambridge, England
Focus	Open-source silicon, RISC-V

LowRISC

LowRISC is an open-source hardware project that develops a foundational system-on-chip and associated toolchain focused on the RISC-V instruction set. It collaborates with academic institutions such as the University of Cambridge and industry partners like Google and SiFive to advance a free-software approach to silicon design, verification, and tooling. LowRISC engages with standards and hardware communities including RISC-V International, CHIPS Alliance, and the Open Compute Project to influence open hardware ecosystems.

History

LowRISC began as an academic initiative at the University of Cambridge in the early 2010s, emerging amid interest from projects like Berkeley RISC-V and movements involving organizations such as IBM, ARM Holdings, and Intel. Early collaborators included researchers affiliated with ETH Zurich, Imperial College London, and the University of Cambridge Computer Laboratory. Funding and partnerships came from entities such as Google, Xilinx, and research grants tied to programs at the Engineering and Physical Sciences Research Council and collaborations with DARPA research programs. LowRISC contributed to discussions alongside projects at Berkeley Lab and events like FOSDEM and Open Source Summit. Milestones included silicon tape-outs, participation in standards forums such as RISC-V International meetings, and public demonstrations at conferences like Hot Chips and Embedded Systems Week.

Architecture and design

LowRISC developed an open SoC platform that integrates a RISC-V core with system-level components and verification infrastructures. The design draws from prior academic work at UC Berkeley and industrial implementations by firms like SiFive and Western Digital. Architectural elements include a tile-based CPU subsystem, debug and tracing blocks compatible with tools from Arm Ltd. ecosystems, and peripheral interconnects informed by efforts at OpenCores and the Apache Software Foundation. The project leverages hardware description languages and toolchains including Chisel from UC Berkeley and SpinalHDL research, and verification methodologies influenced by SystemVerilog and formal methods practiced at MIT and Microsoft Research. LowRISC emphasizes modularity to interoperate with tooling from GCC, LLVM, QEMU, and GDB as well as boot and firmware projects associated with U-Boot and the Linux Foundation.

Open-source hardware and licensing

LowRISC advocates permissive licensing models adapted from software provenance seen at Free Software Foundation and Apache Foundation. It participates in licensing discussions alongside projects such as OpenPOWER Foundation and communities at the Open Source Hardware Association. The project releases RTL, verification suites, and tooling under licenses that aim to align with work by GitLab and GitHub hosted collaborations, and addresses legal frameworks influenced by cases and policies debated in venues like European Commission policy consultations and standards committees at IEEE Standards Association. Licensing choices intersect with contributions from companies like Google and academic institutions such as Stanford University.

Implementations and projects

LowRISC's reference designs and tooling have been used in silicon developments and FPGA prototypes alongside vendors such as Xilinx, Intel Corporation, and Microsemi. Implementations include tape-outs and FPGA boards showcased with partners including SiFive, Western Digital, and research groups at ETH Zurich. The project has interfaced with ecosystem projects like OpenTitan, CHIPS Alliance efforts, and boot/firmware collaborations with Coreboot and Trusted Firmware contributors. It has been demonstrated at industry showcases such as Design Automation Conference and research symposia hosted by ACM and IEEE chapters.

Community and governance

LowRISC operates with a governance model that engages contributors from academia and industry, drawing advisory input from organizations such as RISC-V International, CHIPS Alliance, and corporate partners including Google and Western Digital. Community engagement occurs on platforms like GitHub, mailing lists connected with FOSDEM communities, and in working groups resembling structures used by the Linux Foundation and Apache Software Foundation. Contributors include researchers and engineers from institutions such as University of Cambridge, UC Berkeley, ETH Zurich, and companies including SiFive and Xilinx. Governance debates mirror those seen in bodies like IETF and W3C regarding open standards, contribution policies, and project roadmaps.

Impact and reception

LowRISC has influenced open-source silicon discourse alongside prominent initiatives like Berkeley RISC-V, OpenTitan, and CHIPS Alliance, affecting adoption by academic groups at MIT, Stanford University, and industrial teams at Google and Western Digital. Analysts from firms such as Gartner and coverage in venues like IEEE Spectrum, The Register, and Ars Technica have cited LowRISC when discussing open hardware viability and RISC-V ecosystem growth. The project’s work on verification, tooling, and permissive releases has been referenced in academic publications indexed by ACM Digital Library and arXiv. Broader impacts are visible in collaborations with fab partners including TSMC and GlobalFoundries and in education efforts at universities like Imperial College London and University of Cambridge.

Category:Open-source hardware Category:RISC-V