PSL

PSL
Name	PSL
Type	Professional/Technical Standard
Established	1990s
Country	International

PSL

PSL is a formal specification language and standard used for expressing temporal constraints, requirements, and properties in hardware design, verification, and formal methods. It integrates with hardware description languages and verification tools, enabling engineers to state assertions, temporal relationships, and system behaviors for automated checking and synthesis. PSL is adopted by industry consortia and tool vendors and appears in workflows alongside synthesis, model checking, and simulation environments.

Definition and Overview

PSL originated as a property specification language that augments register-transfer level descriptions with temporal and logical constructs for asserting system properties. It complements languages and standards such as Verilog, VHDL, SystemVerilog, SVA, and UVM by providing patterns for liveness, safety, and stimulus-response relationships. PSL provides operators and constructs influenced by research from institutions like Cadence Design Systems, Synopsys, Intel Corporation, and academic groups at Stanford University and University of California, Berkeley. The language's semantics have been formalized to interoperate with model checkers such as NuSMV, SPIN, and Cadence JasperGold.

History and Development

PSL development traces to industry and academic collaborations responding to scaling verification challenges in the 1990s, alongside efforts that produced standards like IEEE 1364-2001 and IEEE 1076-1993. Early contributors included engineers from IBM, Texas Instruments, and research groups at Carnegie Mellon University and Massachusetts Institute of Technology. Standardization efforts involved consortia such as Accellera and later interactions with IEEE working groups that shaped complementary standards. Tool support expanded with companies including Mentor Graphics and initiatives at Imperas and university-driven model-checking projects, while benchmark suites from International Conference on Computer-Aided Verification participants helped drive adoption.

Structure and Rules

PSL's syntax combines Boolean, temporal, and sequential operators to express complex properties applied to signals and interfaces described in Verilog or VHDL modules and components in SystemC environments. Core constructs include temporal operators comparable to those in CTL, LTL, and regular-expression-like sequences used in SMV-based checking. The language defines finite and infinite-trace semantics relevant to tools such as Cadence Incisive and formal engines like JasperGold and OneSpin. Integration rules govern how PSL assertions are attached to modules in designs produced by teams using flows from ARM Holdings implementations or Intel microarchitecture verification labs, and how assertions interact with simulators from Synopsys and emulators like Mentor Veloce.

Applications and Use Cases

PSL is used to specify functional correctness properties in processor cores from vendors such as ARM, Intel Corporation, and AMD, and in system-on-chip projects from companies like Qualcomm and Broadcom. It supports assertion-based verification in hardware verification methodologies including OVM and UVM, and is applied in model checking campaigns at conferences such as Design Automation Conference and International Symposium on Formal Methods. PSL properties are used in formal equivalence checking for IP integration in supply chains involving TSMC and GlobalFoundries, and in safety-critical electronic control systems in automotive programs by Bosch and Continental AG. PSL also appears in academic research on synthesis, runtime monitoring, and verification tools developed at ETH Zurich and University of Cambridge.

Criticism and Controversies

Critics have pointed to fragmentation among property languages, noting overlaps and differences between PSL, SVA, and proprietary assertion dialects from vendors like Synopsys and Cadence. Debates at standards forums including Accellera meetings and panels at International Conference on Computer-Aided Verification have addressed semantic mismatches between tools such as NuSMV and SPIN and differing interpretations of finite versus infinite trace semantics. Industry adopters such as IBM and Intel have discussed trade-offs between expressiveness and tool performance during formal verification of complex designs presented at Design Automation Conference sessions. Concerns also arise in qualification contexts for automotive and aerospace standards where organizations like ISO and RTCA require traceability and tool certification, prompting scrutiny of PSL toolchains from vendors including OneSpin and Cadence.

See also

Verilog VHDL SystemVerilog SVA Accellera IEEE Cadence Design Systems Synopsys Mentor Graphics ARM Intel Corporation AMD Qualcomm Broadcom TSMC GlobalFoundries Design Automation Conference International Conference on Computer-Aided Verification NuSMV SPIN JasperGold OneSpin UVM Ovm Stanford University University of California, Berkeley Carnegie Mellon University Massachusetts Institute of Technology ETH Zurich University of Cambridge IBM Texas Instruments Bosch Continental AG International Symposium on Formal Methods ISO RTCA Cadence Incisive Mentor Veloce Imperas SMV CTL LTL SystemC Design-for-Testability Formal equivalence checking Assertion-based verification Runtime verification Synthesis (hardware)