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| MIPS 24K | |
|---|---|
| Name | 24K |
| Designer | Silicon Graphics, Inc. |
| Architecture | MIPS (microprocessor) MIPS architecture |
| Introduced | 1999 |
| Clock speed | 400–600 MHz (typical) |
| Process | 0.25 μm–0.18 μm |
| Predecessor | MIPS R10000 |
| Successor | MIPS32 |
MIPS 24K The 24K core is a scalar, superscalar reduced instruction set computing microprocessor core originally developed by Silicon Graphics, Inc. and later licensed through MIPS Technologies. It targeted embedded and networking markets and featured enhancements to integer execution, branch prediction, and power/performance tradeoffs, positioning it between the MIPS R10000 family and later MIPS32 designs. The core saw adoption in routers, storage controllers, and consumer devices from firms such as Cisco Systems, NetApp, and NEC.
The 24K was unveiled as part of Silicon Graphics’ effort to supply a high-performance 32/64-bit MIPS core for commercial and embedded systems. It combined lessons from the MIPS R4000 and MIPS R10000 lines with microarchitectural features aimed at improved integer throughput and predictable latency for networking workloads. Key design goals included low interrupt latency for systems by companies like EMC Corporation, reduced power for OEMs such as Sony Corporation, and scalability for licensees including Broadcom and Samsung Electronics.
The core implemented the MIPS III/MIPS32 instruction set architecture with a five-stage pipeline augmented by superscalar issue for integer operations. It incorporated a two-way issue front end, dynamic branch prediction mechanisms influenced by techniques used at Stanford University and University of California, Berkeley, and a register file compatible with operating systems from Microsoft and Red Hat. The 24K employed a Harvard-style split cache hierarchy with separate L1 instruction and data caches and an integrated L2 cache controller used in designs by Hitachi and Fujitsu. Execution units emphasized integer ALU throughput and multiply/divide engines, with coprocessor interfaces enabling BSD-based networking stacks and real-time extensions favored by Wind River Systems.
Licensees produced multiple implementations on processes ranging from 0.25 μm to 0.18 μm, with custom floorplans for companies such as Texas Instruments, Analog Devices, and Motorola. OEM implementations were integrated into system-on-chip products alongside DMA controllers, PCI bridges, and Ethernet MACs used by Juniper Networks and Alcatel-Lucent. Multi-core or multi-threaded adaptations appeared in products by NEC and Toshiba for storage arrays sold to EMC and Hitachi Data Systems. Third-party vendors combined 24K cores with security accelerators from RSA Security and networking accelerators from Marvell Technology Group.
Independent benchmarks by industry groups and OEMs compared the 24K against contemporaries from ARM Holdings, Intel, and PowerPC offerings. The 24K showed competitive Dhrystone and CoreMark results for integer workloads typical of Cisco router control planes and NetApp storage controllers, with measured improvements in branch misprediction penalties relative to earlier MIPS R4000-based designs. In SPECint-style evaluations conducted by platform vendors including IBM and Oracle Corporation the core demonstrated solid single-thread performance while offering lower power envelopes attractive to Apple Inc.-adjacent embedded suppliers. Real-world throughput gains were highlighted in packet-forwarding tests by Ciena and Nortel Networks licensees.
Adoption concentrated in networking, storage, and consumer electronics. Router control planes from Cisco Systems and Juniper Networks employed the 24K in control processors; NAS devices from NetApp and QNAP Systems, Inc. used it for file-serving tasks. Digital televisions and set-top boxes from Samsung Electronics, LG Electronics, and Sony Corporation integrated 24K-based SoCs for middleware and DRM tasks tied to Broadcom silicon. Industrial controllers from Siemens and Schneider Electric used 24K cores for deterministic control, while telecommunications equipment from Ericsson and Alcatel-Lucent embedded 24K designs in signaling processors.
A broad ecosystem supported the 24K, including compilers from GNU Project GCC and commercial toolchains from Green Hills Software and IAR Systems. Debuggers and IDEs by Eclipse Foundation-based vendors and vendor-specific tools from MIPS Technologies aided bring-up. Real-time operating systems such as VxWorks and QNX and embedded Linux distributions provided board support packages used by Red Hat partners. Verification and simulation leveraged platforms from Synopsys, Cadence Design Systems, and emulation from Mentor Graphics.
The 24K played a role in the transition of MIPS cores from workstation origins at Silicon Graphics, Inc. to widespread embedded licensing under MIPS Technologies and later entities. Its architectural lessons influenced later MIPS32 and MIPS64 cores and informed designs by licensees across Asia and North America. As ARM architectures rose in mobile markets through companies like Qualcomm and Apple Inc., the 24K remained relevant in niche networking and storage segments, contributing to intellectual property portfolios acquired by firms including Imagination Technologies and influencing open-source communities around OpenWrt and uClinux.
Category:MIPS microprocessors