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| High Bandwidth Memory | |
|---|---|
| Name | High Bandwidth Memory |
| Abbreviation | HBM |
| Developer | SK Hynix; Samsung; Micron; JEDEC |
| Introduced | 2013 |
| Type | 3D-stacked DRAM |
| Applications | Graphics processing; High-performance computing; AI accelerators; Networking |
High Bandwidth Memory High Bandwidth Memory is a family of 3D-stacked dynamic random-access memory technologies designed to provide very high bandwidth with low power consumption for accelerator-class devices. It was developed through collaborations among SK Hynix, Samsung Electronics, Micron Technology, and standards bodies such as JEDEC to address bandwidth limits in systems like Intel Xeon Phi, NVIDIA Tesla, AMD Radeon, and custom accelerators from Google and Microsoft.
HBM emerged to overcome limitations in traditional DDR3 and DDR4 modules used by platforms such as Intel Core and AMD Ryzen by utilizing wide interfaces and vertical stacking familiar from projects like 3D XPoint and packaging advances seen in TSV research. Early commercial deployments coincided with products from NVIDIA and AMD and paralleled memory initiatives at organizations including ARM Holdings and IBM labs. Adoption grew in data center environments that include deployments by Amazon Web Services and Facebook for workloads similar to those run on Google TPU clusters and in scientific installations such as the Oak Ridge National Laboratory supercomputers.
HBM uses through-silicon vias inspired by research at institutions like MIT and Stanford University and integrates an interposer concept pioneered by companies such as Intel and TSMC. The design stacks DRAM dies atop a base logic die, a method related to techniques used in Xilinx FPGA packaging and earlier work by Freescale and TSMC research partnerships. HBM replaces long parallel traces used in platforms like PCI Express with wide, short channels, a strategy similar to that in NVLink systems developed by NVIDIA and the interconnect concepts promoted by Open Compute Project contributors such as Facebook and Google.
Generations of HBM progressed in tandem with product roadmaps from SK Hynix, Samsung Electronics, and Micron Technology and standardization updates from JEDEC. Major variants include HBM1 used in early AMD FirePro and NVIDIA Quadro solutions, HBM2 appearing in accelerators like NVIDIA Tesla P100 and AMD Vega, and HBM2E and HBM3 found in Supercomputing and AI accelerators from vendors such as Intel and NVIDIA. Each generation increased per-pin data rates, similar evolutionary steps seen in families like DDR5 and storage upgrades such as NVMe.
HBM provides advantages in aggregate throughput, energy per bit, and footprint when compared with discrete DIMMs used by architectures exemplified by Dell EMC and Hewlett Packard Enterprise. High parallelism enables accelerators from NVIDIA, AMD, and custom ASIC designers at Google to achieve sustained performance for workloads analogous to those on TOP500 systems. Lower latency and reduced routing complexity also benefit designs by Cisco Systems and networking equipment suppliers such as Arista Networks. These attributes align with optimization goals pursued by projects at Lawrence Livermore National Laboratory and CERN for simulation and data analysis.
HBM is implemented in graphics cards like AMD Radeon Vega, compute accelerators such as NVIDIA Tesla V100, and machine-learning appliances from firms like Google and Microsoft Azure. Use cases span real-time rendering in studios using tools from Autodesk and Blender Foundation, deep learning training workloads in research labs at Stanford University and Massachusetts Institute of Technology, and high-frequency trading systems deployed by firms in financial centers such as New York City and London. It is also used in network devices from Juniper Networks and in embedded platforms developed by Qualcomm for mobile and edge compute.
Production relies on wafer bonding and TSV processes developed at fabs operated by TSMC, Samsung Foundry, and SK Hynix facilities, building on packaging techniques used in collaborations with Amkor Technology and ASE Group. Manufacturing challenges echo historical scaling issues addressed by Intel fabs and foundry models adopted by GlobalFoundries. Interposer-based mounting leverages silicon interposer work seen in multi-chip modules produced for Xilinx and high-density packages used in Apple devices.
Major partnerships driving HBM adoption include collaborations among AMD, NVIDIA, Intel, and memory suppliers SK Hynix and Samsung Electronics, alongside standardization by JEDEC. Cloud providers like Amazon Web Services, Google Cloud, and Microsoft Azure accelerated use in AI services comparable to deployments by Baidu and Alibaba Group. Consortium-like cooperation mirrors initiatives from OpenAI and industry groups including the Open Compute Project and standards work by IEEE members.
Challenges include cost pressures similar to those encountered by NAND flash manufacturers, yield improvements pursued by TSMC and Samsung Foundry, and thermal management issues that echo cooling solutions developed at NVIDIA and Intel. Future developments point toward wider adoption of HBM3 and beyond, integration with chiplet architectures championed by AMD and packaging innovations from Intel and TSMC, and ecosystem growth influenced by work at institutions such as DARPA and standards evolution at JEDEC. Continued competition with emerging memories like 3D XPoint and architectures favored by hyperscalers such as Google will shape the trajectory of HBM in next-generation systems.
Category:Computer memory