HBM2

HBM2
Name	HBM2
Designer	SK Hynix, Samsung Electronics, Micron Technology, JEDEC
Type	3D-stacked synchronous DRAM
Introduced	2016
Successor	HBM2E

HBM2.

HBM2 is a high-bandwidth memory standard developed to provide wide data buses and low power per bit for use in graphics processing units, networking equipment, supercomputers, machine learning accelerators, and gaming console platforms. It evolved from work by vendors such as SK Hynix, Samsung Electronics, and Micron Technology in coordination with standards bodies like JEDEC and has been integrated into product lines from companies including AMD, NVIDIA, Intel, and Xilinx.

Overview

HBM2 is the second-generation member of a family of vertically stacked memory standards designed to replace or complement traditional DDR4 and GDDR5 memory in bandwidth-sensitive applications. It uses through-silicon vias (TSVs) and silicon interposers to achieve wide parallel interfaces, targeting applications originally pioneered by systems such as Fujitsu K computer and later seen in platforms like the Fugaku project. Adoption was driven by compute-intensive workloads in centers operated by organizations like Lawrence Livermore National Laboratory, Oak Ridge National Laboratory, and hyperscalers such as Google and Amazon Web Services.

Architecture and Specifications

HBM2 stacks multiple DRAM dies on a single interposer and connects them with TSVs, enabling a wide data interface and short signal paths between the memory and a host device such as a graphics processing unit or field-programmable gate array. Its architecture contrasts with designs used by DDR4 and GDDR5, using up to eight DRAM dies per stack and supporting multiple channels per stack. JEDEC specifications define channel widths, transfer rates, and signaling; vendors implemented data rates per pin ranging from 1.2 Gbit/s to 2.0+ Gbit/s in practical products. Key technical elements include pseudo-channeling, multi-channel stacking, and power delivery considerations relevant to designs from Advanced Micro Devices, NVIDIA Corporation, and server vendors such as Dell EMC and Hewlett Packard Enterprise.

Performance and Use Cases

HBM2 delivers very high aggregate bandwidth and lower energy per bit compared with contemporary GDDR5 and DDR4 in similar form factors, making it suited to high-performance graphics in products from Sony and Microsoft consoles, real-time ray tracing accelerators, and large on-chip caches for machine learning inference and training workloads run on systems by Facebook and Microsoft Azure. Large-scale scientific computing clusters at institutions like CERN and national laboratories use HBM2-equipped accelerators for simulations previously constrained by memory bandwidth. Use cases include tensor compute in accelerators from NVIDIA's datacenter GPUs, matrix multiplication in products from Intel's Habana Labs, and networking packet processing in equipment from Cisco Systems and Arista Networks.

Implementation and Compatibility

Integrating HBM2 requires package-level solutions: interposers (silicon or organic), thermal management, and power integrity measures adopted by original equipment manufacturers such as ASUS, MSI, and system integrators like Supermicro. Platform compatibility involves memory controller support and PHY implementations in processors and FPGAs from AMD, Intel, Xilinx, and mobile-to-edge SoC vendors. Board-level tradeoffs include substrate routing complexity compared to discrete GDDR6 modules used by desktop graphics cards from NVIDIA, AMD Radeon Technologies Group, and workstation vendors such as Lenovo and HP. Supply-chain considerations tied to fabs like TSMC and packaging houses influence lead times for designs in products from Apple and bespoke accelerator suppliers.

Industry Adoption and Products

HBM2 has been used in multiple generations of accelerators and GPUs: examples include AMD Vega-based cards, NVIDIA Tesla series accelerators, and enterprise products from Xilinx (now part of AMD). Supercomputing nodes such as those powered by IBM-class designs and accelerator modules for clusters delivered to research centers and cloud providers incorporated HBM2 to meet high-bandwidth demands. OEMs including Dell Technologies and Lenovo Group offered servers with HBM2-equipped accelerators for HPC and AI workloads; networking vendors such as Juniper Networks explored HBM2 in platforms targeting high-throughput packet processing.

Comparison with Other Memory Technologies

Compared with DDR4, HBM2 provides much greater bandwidth per package and reduced energy per bit at the cost of increased packaging complexity and higher initial BOM costs for platforms from vendors like Supermicro and Dell EMC. Against GDDR5 and GDDR6, HBM2 trades raw per-pin frequency for massively wider interfaces and denser per-package capacity, yielding superior multi-threaded throughput for workloads targeted by NVIDIA and AMD accelerators while requiring silicon interposers similar to those used in advanced packages by Intel and TSMC clients. Later standards such as HBM2E and successors aimed to close gaps in per-pin data rate and capacity, competing with emerging technologies from foundries and memory makers like SK Hynix and Micron Technology that also develop alternatives including hybrid memory cube concepts and 3D-stacked DRAM variants used in bespoke acceleration platforms.

Category:Computer memory