EUV Litho Working Group

EUV Litho Working Group
Name	EUV Litho Working Group
Formation	2010s
Type	Industry consortium
Region	Global
Members	Semiconductor manufacturers, equipment vendors, research institutes, consortia

Contents

EUV Litho Working Group is an industry consortium focused on advancing extreme ultraviolet EUV lithography for semiconductor manufacturing. It coordinates research among companies such as Intel Corporation, Samsung Electronics, Taiwan Semiconductor Manufacturing Company, and ASML Holding and research organizations including IMEC, CERN, and National Institute of Standards and Technology. The group interfaces with standards bodies like SEMATECH and International Roadmap for Devices and Systems contributors to accelerate adoption of EUV in production lines at fabs operated by firms such as GlobalFoundries and Micron Technology.

History and Formation

The working group emerged during the late 2000s and early 2010s amid development milestones at ASML Holding and research programs at IMEC and Sandia National Laboratories. Founding participants included representatives from Intel Corporation, Samsung Electronics, Taiwan Semiconductor Manufacturing Company, and consortiums such as SEMATECH and Heterogeneous System Architecture proponents. Early formation paralleled initiatives at International Technology Roadmap for Semiconductors meetings and was influenced by programs at National Institute of Standards and Technology and research collaborations observed at Applied Materials and Tokyo Electron laboratories.

Membership typically spans major foundries like Taiwan Semiconductor Manufacturing Company and Samsung Electronics, equipment suppliers including ASML Holding and Carl Zeiss AG, materials companies such as Dow Chemical Company and JSR Corporation, and research institutes like IMEC and CERN. Governance models mirror those used by SEMATECH and The Linux Foundation, with steering committees, technical subcommittees, and liaison roles connecting to standards bodies like Institute of Electrical and Electronics Engineers and International Electrotechnical Commission. Regional representation includes participants from United States Department of Commerce-linked labs, European Commission-funded programs, and national labs such as Lawrence Berkeley National Laboratory.

Primary objectives include enabling high-volume manufacturing readiness for EUV tools produced by ASML Holding, improving mask infrastructure linked to Carl Zeiss AG optics, and addressing resist materials from firms like TOKYO OHKA KOGYO and JSR Corporation. The scope encompasses source power scaling, pellicle development, and scanner throughput optimization relevant to fabs at Intel Corporation and Samsung Electronics. The group aligns its goals with roadmaps developed by International Roadmap for Devices and Systems contributors and collaborates on metrology issues with National Institute of Standards and Technology.

Technical projects cover resist chemistry improvements involving companies such as Dow Chemical Company and DuPont, pellicle membrane testing referenced against work at Lawrence Livermore National Laboratory, and source lifetime efforts coordinated with Trumpf-affiliated research. Projects include patterned mask qualification with partners like Toppan Printing and mask inspection methods co-developed with KLA Corporation and Applied Materials. Lithography-enabling simulations use tools from Synopsys and Cadence Design Systems, while contamination control trials reference protocols from Sandia National Laboratories.

The working group produces specification drafts that inform standards efforts at Institute of Electrical and Electronics Engineers and International Electrotechnical Commission committees, and technical notes that feed into International Roadmap for Devices and Systems updates. Publications and white papers are typically co-authored by engineers from Intel Corporation, Samsung Electronics, Taiwan Semiconductor Manufacturing Company, and academic partners at Massachusetts Institute of Technology and Stanford University. Guidelines address pellicle transmittance, source spectral purity, and mask defectivity, aligning with inspection criteria used by KLA Corporation and ZEISS partners.

Collaborations with equipment manufacturers such as ASML Holding and materials suppliers like JSR Corporation have accelerated EUV scanner deployment at fabs operated by TSMC and Intel Corporation. Joint projects with research centers including IMEC and National Institute of Standards and Technology influenced yield improvement programs at GlobalFoundries and process integration efforts at Samsung Electronics. The group’s work informs investment decisions by venture entities and capital projects at fabs in regions including Taiwan and South Korea.

Future efforts target higher source power, next-generation pellicles, and multi-beam defect inspection with partners such as KLA Corporation and Applied Materials. Challenges include supply-chain coordination among vendors like ASML Holding and materials firms, mask infrastructure scaling at Toppan Printing, and workforce training in regions served by SEMATECH and IMEC programs. Strategic alignment with roadmaps from International Roadmap for Devices and Systems and standards from Institute of Electrical and Electronics Engineers will shape adoption paths for advanced nodes at fabs operated by Intel Corporation, TSMC, and Samsung Electronics.