Generated by GPT-5-mini| Computer Architecture Letters | |
|---|---|
| Title | Computer Architecture Letters |
| Discipline | Computer architecture |
| Abbreviation | CAL |
| Publisher | IEEE Computer Society |
| Country | United States |
| Frequency | Irregular / Short communications |
| History | 2001–present |
| Issn | 1545-0678 |
Computer Architecture Letters
Computer Architecture Letters is a peer-reviewed venue for brief reports in the field of computer architecture. It publishes short, rapid-communication articles that present experimental results, design notes, microarchitectural innovations, and methodological advances across processor, memory, and system-level topics. The journal serves researchers from institutions such as Massachusetts Institute of Technology, Stanford University, University of California, Berkeley, and industrial laboratories including Intel Corporation, IBM, and Google.
The title was launched in the early 21st century under the auspices of the IEEE Computer Society to complement longer conferences and journals like International Symposium on Computer Architecture and ACM/IEEE International Symposium on Microarchitecture. Its emergence paralleled growth at research centers such as Bell Labs, Lawrence Berkeley National Laboratory, and Microsoft Research, and coincided with shifts driven by the end of Dennard scaling, the rise of multicore processors, and the advent of heterogeneous systems promoted by companies like NVIDIA and AMD. Editorial leadership has included editors affiliated with Carnegie Mellon University, University of Illinois at Urbana–Champaign, and Georgia Institute of Technology, reflecting ties to programs funded by agencies such as the National Science Foundation and the Defense Advanced Research Projects Agency.
The journal focuses on concise communications addressing microarchitecture, instruction-set design, cache and memory systems, pipeline and branch prediction, interconnects, and hardware accelerators. Topics commonly intersect with work from groups at ETH Zurich, Imperial College London, Tsinghua University, and National University of Singapore, and link to advances in domain-specific accelerators developed by Apple Inc., Facebook (Meta Platforms, Inc.), and Alibaba Group. It regularly covers experimental results involving tools and platforms such as GEM5, Simics, RISC-V implementations, and emulation environments used in labs at Princeton University and Cornell University. Cross-cutting subjects include energy-efficient design influenced by projects at Lawrence Livermore National Laboratory and security-oriented microarchitectural analyses inspired by disclosures from researchers at Vrije Universiteit Amsterdam and University of Oxford.
Computer Architecture Letters publishes short-format articles, errata, and brief commentaries following peer review by editors and specialist reviewers drawn from universities and industry, including reviewers from Harvard University, Yale University, University of Michigan, and University of Toronto. The editorial board has included scholars and practitioners who have participated in program committees for venues like Design Automation Conference, International Conference on Architectural Support for Programming Languages and Operating Systems, and USENIX. Manuscripts emphasize reproducibility and often reference datasets and benchmarks originating from communities centered at SPEC, PARSEC, and MiBench.
The journal is indexed in major bibliographic databases and citation services alongside other IEEE publications; its articles appear in aggregation services used by researchers at Stanford University Libraries, Library of Congress, and international repositories maintained by institutions such as Chinese Academy of Sciences. Notable citation networks connect letters published here to influential papers from conferences like International Symposium on Computer Architecture and journals such as IEEE Micro and ACM Transactions on Computer Systems. While not a high-volume venue, its rapid-publication model has produced timely contributions that influenced projects at ARM Holdings, Qualcomm, and public-sector research funded by the European Research Council.
Several brief reports first made public in this venue have seeded larger investigations into speculative execution mitigations linked to disclosures by researchers at Google Project Zero and mitigations evaluated by teams at Intel Corporation and AMD. Other contributions include concise proposals for novel cache coherence techniques later expanded at Massachusetts Institute of Technology and University of California, San Diego, microbenchmarking observations that informed work at Facebook (Meta Platforms, Inc.) and Netflix, and early descriptions of RISC-V implementations that engaged communities at SiFive and University of California, Berkeley.
The publication is available electronically through digital libraries operated by IEEE Xplore and accessible to subscribers at academic institutions such as Columbia University, University of Oxford, and National University of Singapore. Authors affiliated with organizations like Google, Microsoft, and Intel Corporation may deposit preprints in institutional repositories; some letters are discoverable via aggregators used by the Association for Computing Machinery community and national libraries including the National Diet Library (Japan).
Category:Computer science journals Category:IEEE publications