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| Aldec Riviera-PRO | |
|---|---|
| Name | Aldec Riviera-PRO |
| Developer | Aldec, Inc. |
| Released | 1990s |
| Latest release | 2020s |
| Operating system | Microsoft Windows |
| Genre | Electronic design automation |
| License | Proprietary, commercial |
Aldec Riviera-PRO is a commercial verification environment for hardware description languages used in integrated circuit design. It integrates simulation, verification, and debugging capabilities to support complex designs from early functional validation through formal checks and coverage analysis. Riviera-PRO targets users in semiconductor design, field-programmable gate array development, and systems engineering workflows.
Riviera-PRO is positioned among electronic design automation tools alongside ModelSim, VCS (Verilog simulator), Cadence Incisive, Synopsys VCS, and Mentor Graphics Questa. It supports verification methodologies associated with organizations and initiatives such as Accellera, IEEE, Universal Verification Methodology, UVM, and SystemVerilog. The product is used by teams at companies and institutions including Intel Corporation, AMD, Xilinx, NVIDIA, ARM Holdings, Texas Instruments, Broadcom, Qualcomm, Samsung Electronics, STMicroelectronics, Analog Devices, Infineon Technologies, Renesas Electronics, Microchip Technology, National Instruments, IBM, Toshiba Corporation, NXP Semiconductors, Marvell Technology Group, MediaTek, Altera Corporation, Micron Technology, Rambus, Applied Micro Circuits Corporation, Imagination Technologies, Seagate Technology, Western Digital Corporation, Hitachi, Siemens AG, Roche, GE Healthcare, and research groups at Massachusetts Institute of Technology, Stanford University, UC Berkeley, ETH Zurich, University of Cambridge, Imperial College London, EPFL, and Tsinghua University.
Riviera-PRO provides simulation for languages and methodologies tied to IEEE 1364-2001, IEEE 1800-2012, VHDL-2008, and integration with SystemC models. It offers waveform debugging comparable to tools like GTKWave and integrates code coverage metrics similar to those in gcov and lcov workflows. Advanced features include assertions compatible with SVA (SystemVerilog Assertions), transaction-level modeling compatible with TLM 2.0, and co-simulation hooks used in verification flows alongside MATLAB, Simulink, Python (programming language), and Perl. Riviera-PRO supports testbench automation and regression frameworks used by teams following practices from Continuous integration platforms such as Jenkins and GitLab.
The architecture comprises a simulation kernel, compilation frontends, coverage engines, waveform database, and debug GUI components. Compiler frontends parse dialects defined by IEEE Standards Association, and the simulation kernel interoperates with third-party backends like SystemC and Verilog-AMS models. The debug GUI shares concepts with industry products such as Synopsys Verdi and Cadence JasperGold for traceability and signal interrogation. Integration points exist for version control systems like Git, Subversion, and for build systems referencing Make (software), CMake, and scripting via Tcl and Python (programming language).
Riviera-PRO supports file and data formats tied to standards such as VHDL, Verilog, SystemVerilog, SystemC, Verilog-AMS, and assertion languages from IEEE 1800. It reads waveform formats and database schemas compatible with VCD (file format), FSDB, and vendor-specific dump formats used by tools from Cadence Design Systems, Synopsys, Mentor Graphics, and Xilinx. The tool aligns with coverage interoperability guidelines endorsed by Accellera Systems Initiative and complies with verification methodology documents promulgated by UVM 1.1, UVM 1.2, and related standards committees.
Typical applications include functional verification of processors, digital signal processors, network-on-chip designs, protocol IPs, memory controllers, and system-on-chip subsystems used in products by ARM, Intel Corporation, NVIDIA, Broadcom, Xilinx, and Qualcomm. It is applied in verification of standards-driven interfaces like PCI Express, Ethernet, USB, SATA, DDR SDRAM, HDMI, DisplayPort, MIPI Alliance, and PCIe. Academic and industrial research projects at MIT, Stanford University, ETH Zurich, Tsinghua University, and national labs use Riviera-PRO for prototyping, hardware/software co-verification, and formal assertion checking tied to projects funded by agencies like DARPA, NSF, and European Research Council.
The product is offered under proprietary commercial licensing with edition tiers aimed at small teams and enterprise customers. Licensing models mirror those used by other EDA vendors such as Cadence Design Systems, Synopsys, and Mentor Graphics, including node-locked licenses, floating licenses compatible with FlexLM, and enterprise site licenses. Academic licenses and evaluation agreements are made available to universities and research centers like UC Berkeley, Imperial College London, and EPFL under time-limited or feature-limited terms.
Riviera-PRO evolved through releases responding to changes in standards from IEEE committees and interoperability efforts from Accellera. Its roadmap reflects milestones similar to other EDA tools such as ModelSim's expansion, Synopsys VCS feature additions, and the rise of UVM-based methodologies. Development collaborations and user community interactions have involved corporate users like Intel Corporation, ARM Holdings, Xilinx, NVIDIA, and academic contributors from Stanford University, MIT, UC Berkeley, and ETH Zurich.
Category:Electronic design automation software