multiple-gate MOSFET

multiple-gate MOSFET
Name	Multiple-gate MOSFET
Caption	A schematic cross-section of a FinFET, a common type of multiple-gate device.
Classification	Field-effect transistor
First production	Early 2000s
Inventor	Chenming Hu, Hisamoto Daisuke, and other researchers
Related components	Planar MOSFET, Tunnel FET, Nanosheet FET

multiple-gate MOSFET. A multiple-gate MOSFET is a type of field-effect transistor that incorporates more than one gate electrode to control the flow of charge carriers through a semiconductor channel. This architecture was developed to overcome the severe short-channel effects that plague traditional planar MOSFETs as they are scaled to ever-smaller dimensions, a trend dictated by Moore's law. By providing superior electrostatic control of the channel, these devices enable continued performance improvements and power reduction in advanced integrated circuits, forming the foundation for modern microprocessors and memory devices.

History and development

The conceptual foundations for multiple-gate transistors were laid in the late 1980s and 1990s as the semiconductor industry anticipated the physical limits of planar technology. Pioneering work by researchers like Hisamoto Daisuke at the Hitachi Central Research Laboratory, who proposed the DELTA transistor, demonstrated the potential of a non-planar, gate-wrapped structure. Concurrently, teams at the University of California, Berkeley, led by Chenming Hu, extensively modeled and championed the double-gate MOSFET and later the FinFET as essential for scaling. These research efforts, often presented at the International Electron Devices Meeting, gained critical momentum in the early 2000s when major foundries, including Intel Corporation and Taiwan Semiconductor Manufacturing Company, announced the transition to FinFET technology for high-volume manufacturing, marking a pivotal shift in CMOS technology.

Device structure and operation

The core principle of a multiple-gate MOSFET involves surrounding a thin semiconductor channel with gate electrodes on multiple sides. Unlike a planar device where the gate oxide and gate electrode control the channel only from the top, structures like the FinFET use a vertical silicon "fin" with the gate material deposited on its two sidewalls and often over its top, effectively creating a tri-gate configuration. This geometry allows the electric field from the gate to exert a much stronger influence on the entire channel volume, effectively pinching off the flow of electrons or holes with a lower applied voltage. The improved control suppresses undesirable leakage currents that occur when the channel is nominally off, a phenomenon exacerbated in short-channel planar transistors.

Types of multiple-gate MOSFETs

Several distinct architectures fall under the multiple-gate category, each with unique structural features. The double-gate MOSFET, such as the planar double-gate transistor, features two independent gates on opposite sides of an ultra-thin body. The FinFET is the most commercially successful variant, where the gate straddles a thin vertical fin. An evolution of this is the tri-gate transistor, explicitly utilizing the two sidewalls and the top of the fin. More advanced experimental structures include the gate-all-around FET, where the channel is completely encircled by the gate material, as seen in nanowire FETs and nanosheet FETs. The Omega-FET, named for the gate's omega-like shape, provides near-all-around control with a simpler fabrication process.

Electrical characteristics and advantages

The primary electrical advantages stem from enhanced gate controllability and reduced short-channel effects. This translates to a steeper subthreshold slope, allowing the transistor to switch between on and off states more abruptly, which is crucial for reducing static power consumption. The architecture also offers higher drive current per footprint and better mobility due to reduced electric field crowding. These characteristics directly address the challenges posed by Dennard scaling and enable the continued reduction of supply voltage and dynamic power in accordance with International Technology Roadmap for Semiconductors goals, making them indispensable for high-performance and low-power applications.

Fabrication and integration challenges

Manufacturing these complex three-dimensional structures requires significant advancements in lithography and etch processes. Patterning uniform, high-aspect-ratio fins at nanometer-scale pitches pushed the limits of 193-nanometer lithography and necessitated the development of techniques like multiple patterning and later, extreme ultraviolet lithography. Precise control of fin critical dimensions, sidewall roughness, and crystal orientation is paramount for consistent device performance. Integrating these transistors into a full CMOS flow also introduces challenges in source and drain epitaxy, gate stack formation, and interconnect design, requiring extensive research at institutions like IMEC and Semiconductor Research Corporation.

Applications and future prospects

Multiple-gate MOSFETs, primarily FinFETs, are now the workhorse technology in all leading-edge microprocessors from companies like Apple Inc., Qualcomm, and Advanced Micro Devices, as well as in high-density memory devices like SRAM. Their ability to deliver performance at reduced power has been critical for mobile system-on-a-chip platforms and high-performance computing. The future roadmap involves transitioning to even more controlling architectures like the gate-all-around FET to continue scaling beyond the FinFET era. Research is also exploring the integration of these structures with new channel materials such as silicon-germanium or indium gallium arsenide, and novel concepts like negative capacitance FETs, to further push the limits of energy-efficient computing.

Category:Field-effect transistors Category:Semiconductor devices Category:Microprocessor design