fin field-effect transistor

fin field-effect transistor
Name	Fin field-effect transistor
Caption	A three-dimensional schematic of a FinFET, showing the fin, gate, source, and drain.
Classification	Field-effect transistor
Inventor	Chenming Hu, Tsu-Jae King-Liu, Jeffrey Bokor
First production	Intel, 2011
Related components	Planar MOSFET, Gate-all-around FET, Multi-gate field-effect transistor

fin field-effect transistor. A fin field-effect transistor is a type of multi-gate field-effect transistor that represents a fundamental architectural shift from the traditional planar MOSFET. Its three-dimensional design features a thin silicon "fin" that rises vertically from the substrate, with the gate electrode wrapping around three sides of this channel. This structure provides superior electrostatic control over the channel, enabling continued semiconductor device fabrication scaling as defined by Moore's law and addressing critical limitations like short-channel effect and leakage current.

Overview and Basic Structure

The core innovation of the fin field-effect transistor is its non-planar, three-dimensional architecture. The active channel region is formed as a slender, vertical silicon ridge, known as the "fin," etched from the silicon on insulator layer or bulk silicon wafer. A key structural feature is the gate dielectric, typically silicon dioxide or hafnium silicate, which isolates the conductive polysilicon or metal gate from the fin. This gate structure contacts the fin on three sides—the two sidewalls and the top—forming a tri-gate configuration that is a specific implementation of the broader multi-gate field-effect transistor concept. This design stands in contrast to the single, flat interface of the conventional planar MOSFET pioneered at Bell Labs. The source and drain regions are formed at the ends of the fin, with current flowing along the fin height. The critical dimensions, including fin width and gate length, are tightly controlled during lithography processes at foundries like TSMC and Samsung Electronics.

Operation and Electrical Characteristics

In operation, the application of a voltage to the gate electrode creates an inversion layer along the surfaces of the silicon fin, forming a conductive path between the source and drain. The wrap-around gate geometry provides enhanced gate control over the channel potential, which directly suppresses undesirable short-channel effects such as drain-induced barrier lowering and threshold voltage roll-off. This superior control allows for a steeper subthreshold slope, enabling lower operating voltage and significantly reduced off-state current. Consequently, fin field-effect transistors achieve a better balance between dynamic power consumption and static power dissipation compared to their planar predecessors. The drive current is proportional to the total fin height, leading to design strategies involving multiple parallel fins to increase on-current for a given footprint.

Fabrication and Manufacturing

The manufacturing of fin field-effect transistors leverages advanced semiconductor device fabrication techniques but introduces unique process steps. It typically begins with defining the fin patterns using 193-nanometer immersion lithography or, in more advanced nodes, extreme ultraviolet lithography. The fins are then etched using reactive-ion etching into the silicon layer. A critical step is shallow trench isolation to electrically separate adjacent fins. The formation of the high-κ gate dielectric and metal gate stack, a process pioneered by companies like Intel with their high-κ dielectric materials, follows. Spacer formation and epitaxial growth of silicon germanium or strained silicon in the source and drain regions are used to induce channel strain and improve carrier mobility. The entire process flow is compatible with, but more complex than, the established CMOS technology used for planar transistors.

Scaling and Performance Advantages

The primary advantage of the fin field-effect transistor is its scalability, which has extended the viability of Moore's law into the sub-20-nanometer regime as defined by the International Technology Roadmap for Semiconductors. By providing superior electrostatic integrity, it allows for further reduction of the gate length without a proportional increase in leakage current. This enables higher transistor density, improved switching speed, and lower power consumption—key metrics for modern microprocessor and system on a chip designs. The architecture effectively mitigates process variation and random dopant fluctuation issues that become severe in scaled planar devices. These performance gains have been documented in research from institutions like the University of California, Berkeley and have driven adoption across the industry.

Variants and Related Architectures

Several evolved architectures build upon the basic fin field-effect transistor concept. The gate-all-around FET, where the gate material completely surrounds a nanowire or nanosheet channel, is considered a natural successor for further scaling. Other variants include the fork-sheet FET and the complementary field-effect transistor, which aim to reduce cell area. The fully depleted silicon-on-insulator technology shares similar electrostatic benefits. Research at organizations like IMEC and Semiconductor Research Corporation explores these beyond CMOS devices. Furthermore, materials innovation continues, with investigations into channels made from III-V semiconductor compounds or two-dimensional materials like graphene and molybdenum disulfide for future nodes.

Applications and Industry Impact

Since its commercial introduction by Intel in 2011 for their Ivy Bridge (microarchitecture) processors, the fin field-effect transistor has become the workhorse of modern semiconductor industry. It is now the standard transistor architecture used by all major logic device manufacturers, including TSMC, Samsung Electronics, and GlobalFoundries, across nodes from 16/14 nm down to 5 nm and 3 nm. Its adoption has been critical for advancing central processing unit performance in products from Apple Inc. (Apple A series), Qualcomm (Snapdragon), and AMD. The technology is also essential for graphics processing units from Nvidia and memory devices like DRAM. By enabling more powerful and energy-efficient chips, it underpins progress in artificial intelligence, 5G networks, and Internet of things applications.

Category:Field-effect transistors Category:Semiconductor devices Category:Integrated circuits