Universal Chiplet Interconnect Express

Universal Chiplet Interconnect Express
Name	Universal Chiplet Interconnect Express
Other names	UCIe
Developer	Intel, Advanced Micro Devices, Arm Holdings, Google, Meta Platforms, Microsoft, Qualcomm, Samsung Electronics, Taiwan Semiconductor Manufacturing Company
Type	Chiplet interconnect
Date	March 2022
Website	https://www.uciexpress.org

Universal Chiplet Interconnect Express. It is an open industry standard interconnect for connecting multiple silicon dies, or chiplets, within a single package. Developed by a broad consortium of leading industry players, the specification aims to establish a ubiquitous, high-performance, and power-efficient die-to-die interface. This enables a heterogeneous integration approach to system-on-chip design, allowing designers to mix and match chiplets from different foundries and process nodes.

Overview

The initiative was publicly launched in March 2022 by a founding group that included Intel, Advanced Micro Devices, Arm Holdings, Google, Meta Platforms, Microsoft, Qualcomm, Samsung Electronics, and Taiwan Semiconductor Manufacturing Company. The standard builds upon the well-established PCI Express and Compute Express Link protocols to create a complete chiplet ecosystem. Its primary goal is to disaggregate monolithic SoC designs, fostering innovation and reducing time-to-market. This approach is seen as critical for advancing performance in areas like artificial intelligence, data centers, and client computing.

Technical Specifications

The specification defines both a physical layer and a protocol stack. The physical layer supports two form factors: the standard package, optimized for performance, and the advanced package, which enables higher bandwidth density and lower power consumption. Data rates are scalable, with initial implementations targeting speeds comparable to modern SerDes technologies. Key electrical parameters include stringent requirements for bit error rate, signal integrity, and power integrity. The standard also mandates comprehensive test and measurement methodologies to ensure interoperability between chiplets from different vendors.

Architecture and Protocol Layers

The architecture is layered, separating the physical die-to-die interface from the transaction protocols. The physical layer, or UCIe PHY, handles the electrical signaling and link training. The protocol layer directly adopts the widely-used PCI Express and Compute Express Link industry standards for the transaction and link layers. This leverages existing software stacks and ecosystem tools, significantly reducing adoption complexity. The specification also includes sideband channels for critical functions like power management, test access port control, and error reporting.

Use Cases and Applications

Primary applications are found in high-performance computing segments where traditional scaling faces challenges. In data centers, it enables the creation of modular CPUs, GPUs, and AI accelerators by combining specialized chiplets. For client computing, it allows for more flexible SoC designs in laptops and desktop computers. The automotive industry and 5G infrastructure are also key markets, where heterogeneous integration can meet diverse performance and reliability requirements. Companies like AMD with its Instinct accelerators and Intel with its Ponte Vecchio GPU have pioneered similar proprietary approaches.

Comparison with Alternative Technologies

Prior to this standard, chiplet interconnection was dominated by proprietary interfaces, such as Intel's Advanced Interface Bus and AMD's Infinity Fabric. Other emerging standards include Bunch of Wires from the Open Compute Project and CEI-112G-XSR from the Optical Internetworking Forum. The key differentiator is its comprehensive nature, combining a defined physical layer with established, high-level protocols to create a complete ecosystem. While some alternatives may offer advantages in specific metrics like ultra-short reach density, it aims for broader industry adoption by building on the entrenched PCI Express and Compute Express Link software base.

Standardization and Consortium

The standard is managed by the UCIe Consortium, an independent organization established by the founding members. The consortium's structure includes a board of directors, technical working groups, and promotional groups. Its governance model is designed to be open, allowing other companies to join as contributors or adopters. Prominent members now include Broadcom Inc., MediaTek, and SK Hynix. The consortium's activities are aligned with, but distinct from, other standards bodies like PCI-SIG and JEDEC. The goal is to evolve the specification to support future process nodes and emerging application demands, ensuring its longevity as a foundational technology for heterogeneous integration.

Category:Computer buses Category:Computer hardware standards Category:Semiconductor industry