Rome (microprocessor)

Rome (microprocessor)
Name	Rome
Caption	An AMD EPYC processor based on the Rome microarchitecture.
Designer	Advanced Micro Devices
Bits	64-bit
Introduced	2019
Design	Zen 2
Cores	Up to 64
Socket	Socket SP3
Predecessor	Naples
Successor	Milan

Rome (microprocessor). Rome is the codename for the second generation of AMD's EPYC server and workstation microprocessors, based on the Zen 2 microarchitecture. Launched in August 2019, it represented a major leap in core count, performance, and energy efficiency for the data center market. The introduction of Rome solidified AMD's competitive resurgence against rival Intel in the high-performance server segment.

Overview

The Rome processor family was formally unveiled by AMD CEO Lisa Su at a launch event in San Francisco. It was a direct successor to the first-generation Naples platform and was built using a groundbreaking Chiplet design and an advanced 7 nm manufacturing process. Key innovations included the separation of the central I/O die from the core compute dies, a move that significantly improved yield and scalability. This generation also introduced support for PCIe 4.0, doubling the available bandwidth for storage and networking devices compared to previous platforms.

Architecture

The Rome architecture is a multi-chip module design centered on the Zen 2 core. It utilizes up to eight 7 nm compute dies, each containing up to eight cores and 32 MB of L3 cache, connected via AMD Infinity Fabric to a central 14 nm I/O die. This I/O die, manufactured by GlobalFoundries, houses the memory controller supporting eight channels of DDR4 memory, 128 lanes of PCIe 4.0, and other system interfaces. The disaggregated design allowed AMD to optimize each die for its specific function, improving overall performance per watt. The architecture also featured enhanced security with AMD Secure Memory Encryption and AMD Secure Encrypted Virtualization.

Performance and features

Rome processors delivered substantial performance gains, with SPECint benchmarks showing up to a 50% improvement in instructions per cycle over the previous Naples generation. The top-tier model, the EPYC 7742, offered 64 cores and 128 threads, setting new records in multi-threaded workloads for high-performance computing and cloud computing. The integrated support for PCIe 4.0 provided critical advantages for artificial intelligence workloads and fast NVMe storage arrays. These features made Rome highly attractive for deployments in major hyperscale environments operated by companies like Amazon Web Services and Microsoft Azure.

Manufacturing and process

The compute dies for Rome were manufactured by Taiwan Semiconductor Manufacturing Company using its industry-leading 7 nm FinFET process technology. This node shrink from the previous 14 nm/12 nm processes was instrumental in achieving higher transistor density and greater energy efficiency. The separate I/O die was produced by GlobalFoundries on its 14 nm process, a strategic decision that leveraged different foundry strengths. The chiplet approach itself was a pioneering manufacturing strategy that would influence subsequent designs across the industry.

Market positioning and competition

Rome was positioned as a high-core-count, high-value alternative to Intel's contemporary Xeon Scalable processors, notably the Cascade Lake family. AMD's aggressive pricing and superior core density put significant pressure on Intel, which was struggling with its own 10 nm process delays. Rome gained rapid adoption in the server market, with major OEMs like Dell Technologies, Hewlett Packard Enterprise, and Lenovo launching extensive platforms. Its success was a key factor in AMD achieving its highest server market share in over a decade.

Variants and successors

The Rome family included numerous SKUs targeting different market segments, from single-socket workstations to dual-socket servers. It was succeeded in March 2021 by the Milan generation, which was based on the refined Zen 3 microarchitecture. Milan offered further performance improvements, particularly in latency-sensitive tasks, while maintaining socket compatibility with Rome via the Socket SP3 infrastructure. The architectural principles and chiplet strategy pioneered by Rome continued to evolve in later generations like Genoa and beyond.

Category:AMD microprocessors Category:Server microprocessors Category:2019 introductions