Power ISA

Power ISA
Name	Power ISA
Designer	IBM, Freescale Semiconductor, Power.org
Bits	32-bit, 64-bit
Introduced	0 2006
Version	3.1B (2020)
Type	Load–store architecture, RISC
Encoding	Fixed, variable
Endianness	Bi-endian
Page size	4 KB, 64 KB
Extensions	Vector Scalar Extension, Transactional Memory
Predecessor	PowerPC

Power ISA. It is a reduced instruction set computer (RISC) instruction set architecture (ISA) derived from the earlier PowerPC specification. Developed and stewarded by the OpenPOWER Foundation, it is a prominent architecture in high-performance computing, enterprise servers, and embedded systems. The ISA is known for its scalability, robust feature set, and its transition to an open standard, enabling broad community and commercial development.

History and development

The architecture originated from the collaboration between IBM, Apple Inc., and Motorola in the early 1990s, which created the PowerPC architecture. Following the dissolution of the AIM alliance, IBM continued to evolve the technology for its POWER server line. In 2006, the unified Power ISA was formally defined, merging the Book E specification for embedded use with the server-focused POWER Architecture. Key governance later shifted to the OpenPOWER Foundation, a consortium founded by IBM, Google, NVIDIA, and Mellanox Technologies to promote open collaboration. Major revisions include POWER7, POWER8, and POWER9 implementations, with the ISA becoming fully open-sourced in 2019.

Architecture overview

The design follows a load–store architecture principle and is fundamentally a RISC design. It supports both 32-bit and 64-bit execution modes and operates as a bi-endian architecture, though little-endian mode is dominant in modern Linux deployments. A defining feature is its modularity, with required base instruction classes and numerous optional facilities like the Vector Scalar Extension (VSX) for high-performance floating-point and SIMD operations. The architecture also emphasizes virtualization and reliability, with features for partitioning and advanced error-correcting code memory. It implements a weak memory consistency model and supports very large physical and virtual address spaces.

Instruction set

The instruction set uses both fixed-length 32-bit and variable-length instruction encoding. Base operations include integer, floating-point, load/store, and control flow instructions. Significant optional extensions include the AltiVec/VMX single instruction, multiple data (SIMD) unit, later superseded by the more comprehensive Vector Scalar Extension. Other key extensions are the Transactional Memory facility for hardware lock elision and the Embedded Book E extensions for control systems. The ISA provides sophisticated branch handling, condition register operations, and multiple levels of storage control instructions for system software.

Implementations

Major implementations are the POWER series of server processors from IBM, such as those in the IBM Power Systems line. The PowerPC family, used historically in Apple Macintosh computers and contemporary devices like the Xbox 360 and Wii, are earlier implementations. Modern embedded and high-performance computing designs include the POWER-based processors in the Summit and Sierra supercomputers. The open-source model has spurred new implementations like the Microwatt core and commercial designs from members of the OpenPOWER Foundation.

Software and ecosystem

The primary operating system is Linux, with major distributions like Red Hat Enterprise Linux and SUSE Linux Enterprise Server offering full support. The AIX and IBM i operating systems from IBM are historically significant. Key development toolchains include the GNU Compiler Collection (GCC) and the LLVM compiler infrastructure. A rich software stack runs on the architecture, including Apache Hadoop, Java, Kubernetes, and advanced scientific workloads. The ecosystem is bolstered by firmware standards like OPAL (OpenPower Abstraction Layer) and the Skiroot bootloader.

Licensing and open source initiatives

In August 2019, IBM released the Power ISA v3.0 under a perpetual, royalty-free license to the OpenPOWER Foundation. This move opened the specification for implementation without requiring patent licenses from IBM. The corresponding hardware design for the POWER core was released as the OpenPOWER Foundation. These initiatives are managed through the Linux Foundation, which hosts the open governance model. This allows academic institutions, startups, and companies like Raptor Computing Systems to develop compliant hardware and software freely.

Category:Instruction set architectures Category:OpenPOWER Foundation Category:Power Architecture