PicoArray

PicoArray. It is a massively parallel system-on-chip architecture designed by the British semiconductor company Picochip for high-performance, low-power digital signal processing. The architecture is composed of hundreds of heterogeneous DSP cores interconnected via a deterministic network, enabling it to efficiently handle complex, data-intensive algorithms found in modern wireless communications. Its development was driven by the computational demands of emerging standards like 3GPP LTE and WiMAX, offering a programmable alternative to traditional ASIC designs.

Overview

The fundamental innovation of the architecture lies in its scalable, multiprocessor approach, which partitions complex signal processing tasks across an array of simple, optimized processors. This design philosophy contrasts with conventional von Neumann machines or single, powerful CPUs, providing superior performance per watt for specific workloads. Key applications have historically centered on the PHY layer and baseband processing in telecommunications infrastructure, such as femtocells, picocells, and remote radio heads. Companies like Mindspeed and Intel later engaged with the technology through acquisitions and product integration, aiming to serve markets for small cell deployments.

Architecture

At its core, the architecture features a tiled array of heterogeneous processing elements, each tailored for specific functions like arithmetic logic, multiply-accumulate operations, or control. These tiles are interconnected via a packet-switched, network-on-chip that provides guaranteed latency and bandwidth, which is critical for real-time signal processing. Memory is distributed locally to each processor, minimizing access contention and power consumption compared to shared cache architectures. This deterministic fabric, coupled with tools for static scheduling of both computation and communication, allows developers to reason precisely about timing and performance, a necessity for meeting stringent requirements of standards like W-CDMA and TD-SCDMA.

Development Tools

Programming the array required a specialized integrated development environment that abstracted the hardware parallelism. The primary toolchain included a C compiler, an assembler, a linker, and a graphical simulator for cycle-accurate performance analysis. A critical component was the scheduler, which mapped concurrent software processes onto the physical processor array and configured the communication routes statically at compile time. This approach eliminated the need for a complex operating system or RTOS kernel for resource management, reducing overhead. The tools were designed to give engineers from companies like Alcatel-Lucent and Nokia Siemens Networks a high-level, software-centric workflow for implementing complex protocols.

Applications

Its most significant application domain was in wireless infrastructure, particularly for the development of 4G and 3G base stations and access points. The architecture was used to create chipsets that powered some of the earliest commercial femtocell products, enabling improved indoor coverage and network capacity. Beyond cellular, it found use in other demanding DSP fields such as military communications, software-defined radio, and high-performance computing for specialized algorithms. The technology's ability to be reprogrammed in the field also made it suitable for evolving standards and proprietary waveforms, offering a balance between the flexibility of FPGAs and the efficiency of ASICs.

History

The technology was pioneered by Picochip, a startup founded in 2000 by a team including Peter Claydon and backed by venture capital firms like Atlas Venture and Balderton Capital. The first commercial product, the PC101, was launched in 2003 and targeted the nascent femtocell market. In 2012, the company was acquired by Mindspeed, a move aimed at consolidating assets for the small cell market. Following the acquisition of Mindspeed by Intel in 2014, the technology and intellectual property were integrated into Intel's portfolio for future connectivity solutions, influencing developments within their network processor divisions.

Category:Digital signal processing Category:Computer architecture Category:Multiprocessor computing