IEEE 1149.1

IEEE 1149.1
Title	IEEE 1149.1
Status	Active
Version	Latest revision is IEEE 1149.1-2013
Organization	Institute of Electrical and Electronics Engineers
Committee	IEEE Standards Association
Related standards	IEEE 1149.4, IEEE 1149.6, IEEE 1149.7, IEEE 1532
Domain	Digital electronics, Printed circuit board testing, Integrated circuit design

IEEE 1149.1 is a pivotal technical standard developed by the Institute of Electrical and Electronics Engineers for testing interconnects on printed circuit boards and the internal logic of integrated circuits. Commonly known as the Joint Test Action Group standard or boundary-scan, it defines a methodology for performing structural tests without requiring physical test probes to access every node. The standard has become a cornerstone in electronics manufacturing and design for testability, enabling efficient testing of complex, high-density assemblies prevalent in modern consumer electronics, automotive electronics, and aerospace systems.

Overview and Purpose

The primary purpose of the standard is to address the growing difficulty of physically accessing circuit nodes for testing, a challenge exacerbated by the rise of surface-mount technology, ball grid array packages, and multi-layer printed circuit boards. It establishes a standardized test architecture embedded directly into the integrated circuit silicon, allowing test patterns to be serially shifted into and out of device pins. This capability is crucial for verifying solder joint integrity and detecting manufacturing defects like short circuits and open circuits on assembled boards. The methodology is managed by the JTAG Consortium and is integral to the workflows of major foundries and original equipment manufacturers worldwide.

Technical Architecture

The core architecture mandates the inclusion of a shift register cell at each digital signal pin of a compliant integrated circuit, forming a boundary-scan register that sits between the device's core logic and its input/output pins. These cells are daisy-chained within a device and can be interconnected serially with cells from other devices on a board to create a complete scan path. Additional test data registers, such as a device identification register or a bypass register, are also defined. The architecture operates under the control of a dedicated test logic controller, which is independent of the system's functional central processing unit or microcontroller, ensuring tests can be run even on unpowered or non-functional cores.

Test Access Port (TAP) and State Machine

Control of the boundary-scan logic is performed through a dedicated Test Access Port, a minimal four-wire or optional five-wire interface comprising Test Clock, Test Mode Select, Test Data In, and Test Data Out signals. A finite state machine within each device, known as the TAP controller, interprets the signals on this port to sequence all test operations. This state machine, defined by a specific diagram in the standard, transitions through states for capturing data from pins, shifting data through registers, and updating the output of the scan cells. The simplicity and robustness of this interface have led to its widespread adoption for other purposes, including in-system programming of field-programmable gate arrays and flash memory devices.

Boundary-Scan Instructions

The standard defines a set of mandatory and optional instructions that are shifted into an instruction register to configure the test logic. The mandatory BYPASS instruction allows a device to be skipped in the scan chain to shorten test time, while the SAMPLE/PRELOAD instruction is used to take a snapshot of normal system data or to load test values into the boundary register. The EXTEST instruction is the fundamental command for board-level interconnect testing, enabling the driver and receiver cells to isolate the device's core logic and control pins directly. Other standardized instructions include INTEST for testing the internal logic of a device and IDCODE for reading a manufacturer-specific JEDEC identification code.

Applications and Use Cases

Beyond basic manufacturing test for short circuits on printed circuit boards, the technology is extensively used for in-circuit programming and configuration of complex programmable logic devices, field-programmable gate arrays, and microcontrollers after they are soldered onto a board. In automotive electronics, it supports functional safety standards by enabling robust system-level testing. The aerospace and defense sectors rely on it for testing and maintaining critical avionics systems. Furthermore, it is a fundamental tool for hardware-assisted debug, allowing developers to control and observe processor cores during embedded software development for systems using ARM architecture or Power Architecture processors.

Related Standards and Evolution

The success of the original standard spawned a family of related IEEE Standards Association specifications. IEEE 1149.4 extends the concept to mixed-signal testing of analog circuits. IEEE 1149.6 addresses testing of advanced interconnects using AC-coupled signaling and differential signaling common in high-speed serial links. IEEE 1149.7 defines a reduced-pin version for testing stacked-die system-in-package and multi-core processor environments. For programmability, IEEE 1532 standardizes the use of the TAP for in-system configuration of programmable logic. The core standard itself has been revised multiple times, with significant updates in 2001 and the current version, IEEE 1149.1-2013, which introduced new instructions and clarified the description language.

Category:IEEE standards Category:Digital electronics Category:Electronic test equipment Category:Printed circuit board manufacturing