| superconducting quantum processors | |
|---|---|
| Name | Superconducting quantum processor |
| Type | Solid-state quantum processor |
| Developer | IBM, Google, Rigetti Computing, Intel, D-Wave (annealers) |
| Introduced | 2000s |
| Based on | Superconductivity, Josephson junction |
| Medium | Niobium, aluminium, sapphire, silicon |
| Cryogenics | Dilution refrigerator |
superconducting quantum processors
Superconducting quantum processors are quantum computing devices that use electrically superconducting circuits—most notably Josephson junctions—to realize quantum bits (qubits) and quantum logic. They are a leading platform in experimental Quantum computing and Quantum Physics because they combine lithographic fabrication, microwave engineering, and low-temperature physics to build multi-qubit systems with fast gate speeds and integration potential. Their development drives research in condensed matter physics, materials science, and quantum error correction.
Superconducting quantum processors exploit macroscopic quantum effects that emerge in superconducting circuits, including phase coherence and quantization of flux. The underlying physics links to the theory of Superconductivity (e.g., BCS theory) and to quantum circuit quantization methods introduced by Yurke, Zhou, and others. Key circuit elements include Josephson junctions that provide a nonlinear inductance enabling anharmonic energy spectra used for qubits such as transmons, flux qubits, and phase qubits. These processors test foundational aspects of open quantum systems, decoherence, and quantum measurement while targeting gate-model algorithms like the quantum Fourier transform and variational algorithms.
Common qubit modalities are the transmon qubit, the fluxonium qubit, and planar capacitively shunted qubit variants. Architectures range from fixed-frequency or tunable-frequency qubits coupled via microwave resonators (cQED) to bus-resonator topologies and nearest-neighbor lattices on chip. Commercial and academic implementations appear in prototypes such as IBM's Quantum processors, Google's Sycamore processor, and Rigetti's Aspen series. Topologies exploit microwave resonator couplers, parametric couplers, and tunable couplers developed at institutions including Yale University, University of California, Berkeley, and MIT Lincoln Laboratory.
Control employs shaped microwave pulses produced by arbitrary waveform generators and mixers to implement single- and two-qubit gates via resonant or cross-resonance techniques. Readout is typically performed dispersively using superconducting microwave resonators and parametric amplifiers such as the Josephson parametric amplifier (JPA) or Josephson traveling-wave parametric amplifier (JTWPA) to achieve near‑quantum‑limited amplification. Processors operate in dilution refrigerators reaching millikelvin temperatures supplied by cryogenic vendors and groups at NIST, Google, and IBM. Cryogenic wiring, attenuators, and infrared shielding are critical to suppress thermal photons and preserve coherence.
Single-qubit rotations and two-qubit entangling gates (e.g., cross-resonance, iSWAP, controlled-Z) are implemented with microwave drives and flux pulses. Gate performance is characterized by metrics like fidelity measured via randomized benchmarking and quantum process tomography. Dominant error sources include dielectric and surface loss, quasiparticle poisoning, flux noise, two-level system defects (two-level systems), and readout-induced backaction. Coherence times (T1 relaxation, T2 dephasing) have improved from nanoseconds to hundreds of microseconds in optimized devices; ongoing work compares materials and geometries from groups at UC Santa Barbara and Princeton University.
Scaling to hundreds or thousands of qubits faces engineering and theoretical challenges: crosstalk, microwave routing, thermal management in cryogenics, yield and fabrication variability, and classical control electronics. Integration strategies include 3D integration, cryo-CMOS control, and quantum interconnects using microwave or optical links. Error correction efforts focus on bosonic codes, surface codes, and cat codes implemented on superconducting hardware; notable demonstrations include small logical qubits and repetition-code experiments at Google and IBM. Achieving fault tolerance demands qubit fidelities and gate error rates compatible with threshold theorems from quantum error correction theory.
Fabrication uses thin-film superconductors (aluminium, niobium, niobium nitride) patterned by photolithography and electron-beam lithography to define junctions and interconnects. Junctions are typically Al/AlOx/Al fabricated by shadow evaporation; multilayer processes and flip-chip bonding support crossovers and 3D stacks. Material research targets loss reduction via substrate cleaning, surface passivation, and interface engineering; institutions like NIST, Sandia National Laboratories, and university cleanrooms contribute process innovations. Device engineering also addresses packaging, magnetic shielding, and infrared filtering to mitigate decoherence mechanisms.
Superconducting processors are applied to quantum simulation, optimization (via variational quantum eigensolver and quantum approximate optimization algorithm), and benchmarking primitives demonstrating quantum supremacy claims such as Google's Sycamore sampling experiment. Performance metrics include gate and readout fidelity, quantum volume (pioneered by IBM), circuit depth achievable before decoherence, and error per two-qubit gate. Industry roadmaps from IBM, Google Research, and start-ups like Rigetti Computing emphasize scaling, improved coherence, and integration with classical control for Near-Term Intermediate-Scale Quantum (NISQ) applications.
Category:Quantum hardware Category:Superconducting devices