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| SMT Competition | |
|---|---|
| Name | SMT Competition |
| Genre | Scientific competition |
| Established | 2005 |
| Organizer | International Satisfiability Modulo Theories community |
| Frequency | Annual |
SMT Competition The SMT Competition is an annual international contest for automated theorem provers in the domain of Satisfiability Modulo Theories, attracting participants from research groups, industrial laboratories, and open-source projects. It evaluates performance of solvers on standardized benchmarks drawn from academic research, industrial verification, and synthesis tasks, informing development at institutions such as Stanford University, Microsoft Research, Google Research, ETH Zurich and Carnegie Mellon University. The event is closely associated with conferences and workshops like CAV and CADE and often coordinated with organizers from INRIA and NASA Ames Research Center.
The competition measures solver capabilities on logical fragments combining propositional logic with theories such as arithmetic, arrays, bit-vectors, and uninterpreted functions. Entries include solvers implementing engines influenced by paradigms developed at Princeton University, Massachusetts Institute of Technology, University of Oxford, University of Cambridge, and University of California, Berkeley. Results are used by developers affiliated with projects from Facebook AI Research, Amazon Web Services, Siemens and national laboratories like Lawrence Livermore National Laboratory to benchmark advances in SMT technology.
The event traces roots to early decision-procedure evaluations from groups at Microsoft Research and SRI International and evolved alongside milestones such as the development of the DPLL(T) framework, influential in publications from Google Research and EPFL. Key editions coincided with major releases of solvers from teams at Z3 team at Microsoft Research and CVC4 developers at Stanford and NYU and had participation from projects originating at University of Freiburg and University of Iowa. Conference alignments included program committees of FLoC-associated meetings and workshops held in conjunction with IJCAR and SAT.
The contest is organized into tracks that reflect input languages and theory combinations, with categories for quantifier-free logics, quantified logics, and application-specific suites used by groups at NVIDIA Research, IBM Research, Google DeepMind and Intel Labs. Entrants submit binaries tested on clusters maintained by institutions such as ETH Zurich and University of Oxford Computer Science Department under time and memory limits inspired by benchmarking practices at SPEC and TACAS. Track rules are drafted by steering committees involving representatives from INRIA, CNRS, Max Planck Institute for Informatics and University of Texas at Austin.
Benchmarks comprise problem sets contributed by academic teams at University of Illinois Urbana-Champaign, University of Toronto, Tel Aviv University, and industrial partners like ARM Research and Bosch Research. Benchmarks cover formats standardized by the input language developed alongside tools from SMT-LIB initiative and draw on application domains from NASA Jet Propulsion Laboratory, Toyota Research Institute, and Honeywell. Scoring uses measures for time-to-solution, correctness, and problem coverage, comparable to metrics used in SAT Competition and other evaluation campaigns organized by CADE and CAV.
Notable participating systems trace heritage to research at Microsoft Research, Stanford University, New York University, University of Iowa, University of Freiburg, and Google Research. Examples include engines related to Z3 teams, projects originating from University of Cambridge labs, and open-source efforts involving contributors from MIT and ETH Zurich. Toolchains often integrate parsers and translators developed at SMT-LIB collaborators and performance analysis tools maintained by groups at University of Oxford and Princeton University.
Outcomes inform verification workflows deployed in industry by companies such as Intel Corporation, Qualcomm, Siemens, and Toyota, and influence academic research programs at Harvard University, University of California, Los Angeles, University of Washington, and Imperial College London. Results have driven improvements in software model checking projects like those from Microsoft Research and NASA Ames Research Center and have been cited by teams working on program synthesis at Google DeepMind and Facebook AI Research. Benchmark-driven enhancements have also been adopted in hardware verification efforts at ARM Holdings and Broadcom.
Challenges include scaling to industrial-size verification problems encountered by Siemens and Honeywell, supporting richer theories used by projects at Toyota Research Institute and Bosch Research, and integrating machine-learning-driven heuristics explored at DeepMind and Facebook AI Research. Future directions discussed by organizers affiliated with INRIA, CNRS, Max Planck Society, and University of Cambridge emphasize cross-benchmark portability, reproducibility practices adopted by SPEC and enhanced interoperability with proof assistants such as those from Coq development team and Isabelle groups. Continued collaboration with industry partners like Microsoft, Google, and IBM aims to broaden benchmark collections and evaluation methodologies.
Category:Competitions