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| SAMPA chip | |
|---|---|
| Name | SAMPA chip |
| Developer | CERN |
| Introduced | 2000s |
| Type | Mixed-signal ASIC |
| Process | CMOS |
| Application | Particle detector readout, high-energy physics |
SAMPA chip The SAMPA chip is a mixed-signal application-specific integrated circuit developed for front-end readout in high-energy physics experiments. It integrates analog preamplifiers, shapers, analog-to-digital conversion, and digital serialization to interface detector sensors with data-acquisition systems. SAMPA was designed to meet the stringent timing, radiation tolerance, and bandwidth requirements of modern collider and fixed-target experiments.
SAMPA was created to serve experiments requiring dense channel integration and low-noise performance, such as those at CERN, European Organization for Nuclear Research experiments, and large-scale collaborations like ALICE, ATLAS, and CMS. The chip addresses needs in experiments using gaseous detectors, silicon trackers, and time-projection chambers, providing interfaces compatible with readout frameworks used by collaborations including LHCb and detector consortia at facilities like CNGS and European XFEL. SAMPA’s development intersected with industrial partners and microelectronics institutes such as STMicroelectronics, TSMC, and academic groups at University of Bonn and University of Geneva.
SAMPA’s architecture combines low-noise analog front ends with digital back ends implemented in complementary metal–oxide–semiconductor fabrication processes pioneered by foundries such as TSMC and GLOBALFOUNDRIES. The front end typically includes charge-sensitive preamplifiers, programmable shaping times, and baseline restoration circuits inspired by designs used in WA98 experiment, ALICE ITS upgrades, and CMS Tracker. Analog-to-digital conversion uses successive-approximation or pipeline techniques comparable to converters developed for ATLAS Inner Detector electronics and NA62 experiment readout. The digital section supports zero suppression, buffering, and event framing compatible with protocols adopted by trigger and DAQ systems used at Large Hadron Collider experiments. Power management, clock distribution, and redundancy draw from standards employed by European Strategy for Particle Physics initiatives and microelectronics reliability practices from ESA projects.
SAMPA performs charge collection, amplification, shaping, digitization, and serialization for multi-channel sensor arrays. It implements noise-optimization techniques similar to those in designs for ATLAS Liquid Argon Calorimeter and timing features derived from developments at CERN Medipix and Timepix projects. The chip supports per-channel calibration, threshold tuning, and common-mode correction akin to methods used in ALICE TPC calibration and LHCb RICH front-end electronics. Data formatting, error-checking, and link management are interoperable with optical link standards used by Versatile Link and back-end systems used in Data Acquisition Systems of experiments like Belle II and NOvA experiment.
SAMPA’s development involved collaborations among laboratories, universities, and industry partners, reflecting cooperative models seen in projects like CERN-RD group initiatives and collaborations such as European Collaboration on Detector Development. Development milestones paralleled timelines of major detector upgrades for LHC Run 2 and LHC Run 3 and drew on expertise from groups that contributed to ALICE upgrade, ATLAS upgrade, and CMS upgrade programs. Funding and oversight included agencies comparable to European Commission, CNRS, INFN, DESY, and national research councils active in detector R&D. Academic contributors included research teams from University of Birmingham, University of Cambridge, Universiteit Antwerpen, and Kraków AGH University of Science and Technology.
SAMPA has been deployed in front-end electronics for time-projection chambers, silicon strip detectors, and micropattern gaseous detectors used in experiments at CERN, GSI, and synchrotron facilities such as ESRF and Diamond Light Source. Its use cases mirror application domains of chips used in ALICE TPC upgrade readout, CBM experiment prototypes, and detector systems at FAIR and J-PARC. Integration examples include hybrid boards, front-end modules, and data-concentrator units compatible with crate standards used at CERN test beams and beamlines like those at PS Complex.
Measured performance metrics for SAMPA include equivalent noise charge, dynamic range, linearity, channel-to-channel crosstalk, and radiation tolerance comparable to front-end ASICs such as those in CARIOCA family, BEETLE chip, and VFAT. Radiation-hardening strategies reflect practices from the RD53 collaboration and radiation qualification campaigns following methods used for ATLAS Pixel and CMS Pixel electronics. Benchmarks often compare SAMPA’s throughput and latency against contemporary mixed-signal ASICs used in collider experiments and neutrino detectors, and its power consumption and area per channel are evaluated alongside designs from IHEP and commercial low-power ASIC efforts at STMicroelectronics.
Production flows for SAMPA follow CMOS mask set fabrication, wafer testing, dicing, and packaging processes common to ASIC productions for experiments like ALICE and LHCb. Packaging options include ceramic and plastic QFN or BGA formats used by collaborations in harsh-environment deployments such as CERN test benches and beamline installations at PSI and TRIUMF. Reliability qualification uses accelerated aging, thermal cycling, and radiation-hardened screening similar to protocols from ESA and high-reliability programs at Oak Ridge National Laboratory and Brookhaven National Laboratory. Yields and lot-to-lot variability are managed through collaboration with commercial foundries and university cleanroom facilities.
Category:Front-end electronics